Electrical characteristic of InGaAs multiple-gate MOSFET devices

Author(s):  
Cheng-Hao Huang ◽  
Yiming Li

Author(s):  
Cha-Ming Shen ◽  
Tsan-Cheng Chuang ◽  
Jie-Fei Chang ◽  
Jin-Hong Chou

Abstract This paper presents a novel deductive methodology, which is accomplished by applying difference analysis to nano-probing technique. In order to prove the novel methodology, the specimens with 90nm process and soft failures were chosen for the experiment. The objective is to overcome the difficulty in detecting non-visual, erratic, and complex failure modes. And the original idea of this deductive method is based on the complete measurement of electrical characteristic by nano-probing and difference analysis. The capability to distinguish erratic and invisible defect was proven, even when the compound and complicated failure mode resulted in a puzzling characteristic.



Author(s):  
Chuan Zhang ◽  
Jane Y. Li ◽  
John Aguada ◽  
Howard Marks

Abstract This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.



2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.





Author(s):  
Farah Asyikin Abd Rahman ◽  
Mohd Zainal Abidin Ab Kadir ◽  
Ungku Anisa Ungku Amirulddin ◽  
Miszaina Osman




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