Improvement of junction characteristics of ultra shallow junction with boron-cluster implantation and Ni-silicide for nano-scale CMOS technology

2010 ◽  
Author(s):  
Hong-Sik Shin ◽  
Se-Kyung Oh ◽  
Min-Ho Kang ◽  
In-Shik Han ◽  
Hyuk-Min Kwon ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Shallow Junction ◽  
Boron Cluster ◽  
Nano Scale

Nano-scale Depth Profiles of Electrical Properties of Phosphorus Doped Silicon for Ultra-Shallow Junction Evaluation

2021 ◽  
pp. 1-1
Author(s):  
Hung-Yuan Chang ◽  
Yew-Chung Sermon Wu ◽  
Chia-He Chang ◽  
Kun-Lin Lin ◽  
Abhijeet Joshi ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Shallow Junction ◽  
Depth Profiles ◽  
Nano Scale ◽  
Doped Silicon ◽  
Phosphorus Doped

Effects of Carbon Co-Implantation on Transient Enhanced Diffusion and Performances of the Phosphorus Doped Ultra-Shallow Junction Nano NMOSFET

2013 ◽  
Vol 284-287 ◽  
pp. 98-102
Author(s):  
Hung Yu Chiu ◽  
Yean Kuen Fang ◽  
Feng Renn Juang
Keyword(s):  
Cmos Technology ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Technology Applications ◽  
Implantation Process ◽  
Phosphorus Doped

The carbon (C) co-implantation and advanced flash anneal were employed to form the ultra shallow junction (USJ) for future nano CMOS technology applications. The effects of the C co-implantation process on dopant transient enhanced diffusion (TED) of the phosphorus (P) doped nano USJ NMOSFETs were investigated in details. The USJ NMOSFETs were prepared by a foundry’s 55 nano CMOS technology. Various implantation energies and doses for both C and P ions were employed. Results show the suppression of the TED is strongly dependent on both C and P implantation conditions. Besides, the mechanisms of P TED and suppression by C ion co-implantation were illustrated comprehensively with schematic models.

Considerations and Optimization of Measurement Accuracy of Capacitance in Nano-Scale CMOS Technology

2012 ◽  
Vol 4 (9) ◽  
pp. 924-929 ◽  
Author(s):  
Si Han Cao ◽  
Xiao Peng Yu ◽  
Yun Pan ◽  
Zheng Shi ◽  
Chang Hui Hu
Keyword(s):  
Measurement Accuracy ◽  
Cmos Technology ◽  
Nano Scale

scholarly journals The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology

2016 ◽  
Vol 67 ◽  
pp. 74-81 ◽  
Author(s):  
Basel Halak ◽  
Vasileios Tenentes ◽  
Daniele Rossi
Keyword(s):  
Cmos Technology ◽  
Nano Scale ◽  
Level Shifters ◽  
The Impact

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

1998 ◽  
Vol 525 ◽  
Author(s):  
J. A. Kittl ◽  
Q. Z. Hong ◽  
H. Yang ◽  
N. Yu ◽  
M. Rodder ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Sheet Resistance ◽  
Cmos Technology ◽  
Successful Implementation ◽  
Optimal Process ◽  
Shallow Junction ◽  
Low Resistance ◽  
Mo Doping ◽  
One Step

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

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