Considerations and Optimization of Measurement Accuracy of Capacitance in Nano-Scale CMOS Technology

2012 ◽  
Vol 4 (9) ◽  
pp. 924-929 ◽  
Author(s):  
Si Han Cao ◽  
Xiao Peng Yu ◽  
Yun Pan ◽  
Zheng Shi ◽  
Chang Hui Hu
2016 ◽  
Vol 67 ◽  
pp. 74-81 ◽  
Author(s):  
Basel Halak ◽  
Vasileios Tenentes ◽  
Daniele Rossi

2006 ◽  
Vol 17 (4) ◽  
pp. 465-489 ◽  
Author(s):  
ELLIS CUMBERBATCH ◽  
SHIGEYASU UNO ◽  
HENOK ABEBE

The continuing down-scaling trend of CMOS technology has brought serious deterioration in the accuracy of the SPICE (Simulation Program with Integrated Circuit Emphasis) device models used in the design of chip functions. This is due to in part to hot electron and quantum effects that occur in modern nano-scale MOSFET devices [13, 25, 28, 33, 34]. The focus of this paper is on modeling quantum confinement effects based on the Density-Gradient (DG) model [6, 9, 14], for application in SPICE. Analytic 1-D quantum mechanical (QM) effects correction formulae for the MOSFET inversion charge and electrostatic potential are derived from the DG model using matched asymptotic expansion techniques. Comparison of these new models with numerical data shows good results.


Author(s):  
Prof. Nikhil Surkar

Semiconductor industry greatly depends on CMOS technology and now needs competent technology with handful benefits. This paper examines and analyzes the modern FINFET technology. This analysis is performed through 9 stages Ring Oscillator equipped with FINFET. Performance is analyzed by comparing the proposed structure with CMOS based 9 stage Ring Oscillator at the nano-scale level of abstraction.


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