Co-Integration of Nano-Scale Vertical- and Horizontal-Channel Metal-Oxide-Semiconductor Field-Effect Transistors for Low Power CMOS Technology

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

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Coulomb Blockade Phenomena in Si Metal-Oxide-Semiconductor Field-Effect Transistors with Nano-Scale Channels Fabricated Using Focused-Ion Beam Implantation

Japanese Journal of Applied Physics ◽

10.1143/jjap.38.7222 ◽

1999 ◽

Vol 38 (Part 1, No. 12B) ◽

pp. 7222-7226 ◽

Cited By ~ 1

Author(s):

Hiroki Kondo ◽

Kenta Izumikawa ◽

Masakazu Sakurai ◽

Shin-ichi Baba ◽

Hirotaka Iwano ◽

...

Keyword(s):

Metal Oxide ◽

Coulomb Blockade ◽

Field Effect ◽

Focused Ion Beam ◽

Field Effect Transistors ◽

Ion Beam ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Nano Scale ◽

Ion Beam Implantation

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High Stable and Low Power 8T CNTFET SRAM Cell

Journal of Circuits System and Computers ◽

10.1142/s0218126620500802 ◽

2019 ◽

Vol 29 (05) ◽

pp. 2050080

Author(s):

M. Elangovan ◽

K. Gunavathi

Keyword(s):

Metal Oxide ◽

Low Power ◽

Field Effect ◽

Field Effect Transistor ◽

Cmos Technology ◽

Metal Oxide Semiconductor ◽

Vlsi Circuits ◽

Oxide Semiconductor ◽

Sram Cell ◽

Effect Transistor

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

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