Parallel time interleaved Delta Sigma band pass analog to digital converter for SOC applications

Author(s):  
Saiyu Ren ◽  
R. Siferd ◽  
R. Blumgold
2019 ◽  
Vol 292 ◽  
pp. 04005
Author(s):  
Miguel A. Lagunas ◽  
Ana Perez-Neira ◽  
José Rubio

In this paper we propose to introduce a new processing scheme in the basic loop of a Delta Sigma (ΔΣ) analog-to-digital converter. This processing confers extra gains of the converter over both the quantization error and the channel noise. This is an advance with respect to all cases found in the literature, where the desired signal is not protected against channel noise. Also, the proposed processing is simple and contrasts with the existing architectures, which produce better quality at the expense of sensitivity to implementation imperfections due to the presence of multiples loops in the corresponding architecture. Furthermore, the in-phase/quadrature components structure of a band pass signal has not been used to improve the performance of ΔΣ converters.


Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.


2018 ◽  
Vol 89 (8) ◽  
pp. 084709
Author(s):  
Zouyi Jiang ◽  
Lei Zhao ◽  
Xingshun Gao ◽  
Ruoshi Dong ◽  
Jinxin Liu ◽  
...  

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