Non-local modeling of impact ionization for optimal device/circuit design in fully depleted SOI CMOS technology

2002 ◽  
Author(s):  
S. Krishnan ◽  
J.G. Fossum
Keyword(s):  
Circuit Design ◽  
Impact Ionization ◽  
Cmos Technology ◽  
Fully Depleted ◽  
Local Modeling ◽  
Non Local ◽  
Soi Cmos

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

2003 ◽  
Vol 24 (4) ◽  
pp. 251-253 ◽  
Author(s):  
Sang Lam ◽  
Hui Wan ◽  
Pin Su ◽  
P.W. Wyatt ◽  
C.L. Chen ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Fully Depleted ◽  
Gate Structure ◽  
Soi Cmos

Fully depleted SOI-CMOS technology for high temperature IC applications

1997 ◽  
Vol 46 (1-3) ◽  
pp. 1-7 ◽  
Author(s):  
B. Gentinne ◽  
J.-P. Eggermont ◽  
D. Flandre ◽  
J.-P. Colinge
Keyword(s):  
High Temperature ◽  
Cmos Technology ◽  
Fully Depleted ◽  
Soi Cmos

scholarly journals High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

2020 ◽  
Vol 10 (3) ◽  
pp. 27
Author(s):  
Andrea Ballo ◽  
Alfio Dario Grasso ◽  
Salvatore Pennisi ◽  
Chiara Venezia
Keyword(s):  
Resonant Frequency ◽  
Performance Optimization ◽  
Cmos Technology ◽  
Second Order ◽  
Silicon On Insulator ◽  
Circuit Performance ◽  
Fully Depleted ◽  
Current Consumption ◽  
28 Nm ◽  
Soi Cmos

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems

2001 ◽  
Vol 45 (4) ◽  
pp. 541-549 ◽  
Author(s):  
D Flandre ◽  
S Adriaensen ◽  
A Akheyar ◽  
A Crahay ◽  
L Demeûs ◽  
...  
Keyword(s):  
High Temperature ◽  
Cmos Technology ◽  
Fully Depleted ◽  
Soi Cmos
Sign in / Sign up

Export Citation Format

Share Document