Low voltage and performance tunable CMOS circuit design using independently driven double gate MOSFETs

2004 IEEE International SOI Conference (IEEE Cat No 04CH37573) SOI-04 ◽

10.1109/soi.2004.1391582 ◽

2005 ◽

Author(s):

A. Kumar ◽

B.A. Minch ◽

S. Tiwari

Keyword(s):

Circuit Design ◽

Low Voltage ◽

Double Gate ◽

Cmos Circuit ◽

And Performance

Download Full-text

Low-voltage analog and mixed-signal CMOS circuit design

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers ◽

10.1109/isscc.2009.4977527 ◽

2009 ◽

Author(s):

Ian Galton

Keyword(s):

Circuit Design ◽

Low Voltage ◽

Cmos Circuit ◽

Download Full-text

A Novel Scaling Theory for Effective Conductive Path Effect of Double Gate (DG) MOSFETs for Nano-Scale CMOS Circuit Design

2008 International Conference on Signal Processing, Communications and Networking ◽

10.1109/icscn.2008.4447218 ◽

2008 ◽

Author(s):

N. B. Balamurugan ◽

K. Sankaranarayanan ◽

V Priyadharsini ◽

M. Ishwarya Devi

Keyword(s):

Circuit Design ◽

Scaling Theory ◽

Double Gate ◽

Cmos Circuit ◽

Conductive Path ◽

Download Full-text

Low-Voltage Low-Power VLSI CMOS Circuit Design

Low-Power Digital VLSI Design ◽

10.1007/978-1-4615-2355-0_4 ◽

1995 ◽

pp. 115-256

Author(s):

Abdellatif Bellaouar ◽

Mohamed I. Elmasry

Keyword(s):

Low Power ◽

Circuit Design ◽

Low Voltage ◽

Download Full-text

Low-voltage and high-speed CMOS circuit design with low-power mode

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) ◽

10.1109/icecs.2015.7440248 ◽

2015 ◽

Author(s):

Yngvar Berg ◽

Omid Mirmotahari

Keyword(s):

Low Power ◽

Circuit Design ◽

Low Voltage ◽

Cmos Circuit ◽

Download Full-text

Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications

2019 Eleventh International Conference on Ubiquitous and Future Networks (ICUFN) ◽

10.1109/icufn.2019.8806167 ◽

2019 ◽

Author(s):

I-Chyn Wey ◽

Chun-Han Chen ◽

Si-Zhan Fang ◽

Heng-Jui Chou

Keyword(s):

Low Power ◽

Circuit Design ◽

Low Voltage ◽

Cmos Circuit ◽

Iot Applications ◽

Download Full-text

A power-performance adaptive low voltage analog circuit design using independently controlled double gate CMOS technology

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328165 ◽

2004 ◽

Author(s):

A. Kumar ◽

S. Tiwari

Keyword(s):

Circuit Design ◽

Analog Circuit ◽

Low Voltage ◽

Cmos Technology ◽

Double Gate ◽

Analog Circuit Design ◽

Power Performance

Download Full-text

Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV

2015 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2015.83 ◽

2015 ◽

Author(s):

Yngvar Berg ◽

Omid Mirmotahari

Keyword(s):

Circuit Design ◽

Analog Circuits ◽

Low Voltage ◽

Download Full-text

Double gate (DG)-SOI ratioed logic with symmetric DG load––a novel approach for sub 50 nm low-voltage/low-power circuit design

Solid-State Electronics ◽

10.1016/j.sse.2004.05.006 ◽

2004 ◽

Vol 48 (10-11) ◽

pp. 1727-1732 ◽

Author(s):

S. Mitra ◽

A. Salman ◽

D.P. Ioannou ◽

C. Tretz ◽

D.E. Ioannou

Keyword(s):

Low Power ◽

Circuit Design ◽

Low Voltage ◽

Double Gate ◽

Power Circuit ◽

Download Full-text

Nano-CMOS circuit design and performance evaluation by inclusion of ballistic transport processes

2009 International Semiconductor Device Research Symposium ◽

10.1109/isdrs.2009.5378261 ◽

2009 ◽

Author(s):

D.C.Y. Chek ◽

M.L.P. Tan ◽

V.K. Arora

Keyword(s):

Performance Evaluation ◽

Circuit Design ◽

Ballistic Transport ◽

Transport Processes ◽

Cmos Circuit ◽

And Performance

Download Full-text

Minimal switching of multiple input multilevel output DC-DC converter

International Journal of Power Electronics and Drive Systems (IJPEDS) ◽

10.11591/ijpeds.v12.i2.pp968-974 ◽

2021 ◽

Vol 12 (2) ◽

pp. 968

Author(s):

Amer A. Chlaihawi ◽

Ameen Al-Modaffer ◽

Hur Jedi

Keyword(s):

Circuit Design ◽

Low Voltage ◽

Electric Circuit ◽

Conversion Ratio ◽

Power Losses ◽

Multiple Input ◽

Voltage Stress ◽

Reduction Number ◽

And Performance ◽

This paper proposes a minimal switching multiple input multilevel output (MS-MIMLO) DC-DC converter. Minimizing the cost of operation is an utmost priority of any electric circuit design. Thus, reduction number of switches that control and manage the operation of feeding power into the MIMLO DC-DC convertors is presented. The proposed MS-MIMLO DC-DC converter exerts many advantages, include high voltage transfer ratio with a small size inductor, reduced power losses and low voltage stress across the semiconductor devices. Beside the highly conversion ratio and efficiency, the characteristics of the proposed converter have a simple configuration with low number of components as well. The MATLAB/Simulink software was implemented to simulate the proposed topology in order to verify the performance of the MS-MIMLO DC-DC converter. The result of simulations demonstrated the benefits of reducing the number of switches without affecting the operation and performance of the MIMLO DC-DC converter circuit.

Download Full-text