Laser Ultrasonic Inspection of Solder Bumps in Flip-Chip Packages Using Virtual Chip Package as Reference

2011 ◽  
Vol 1 (11) ◽  
pp. 1739-1746 ◽  
Author(s):  
Charles Ume ◽  
Jie Gong ◽  
Razid Ahmad ◽  
Abel Valdes
Keyword(s):  
Flip Chip ◽  
Ultrasonic Inspection ◽  
Laser Ultrasonic ◽  
Solder Bumps

scholarly journals Measurement Capability of Laser Ultrasonic Inspection System for Evaluation of Ball-Grid Array Package Solder Balls

2021 ◽  
Vol 18 (4) ◽  
pp. 183-189
Author(s):  
Vishnu V. B. Reddy ◽  
Jaimal Williamson ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Ultrasonic Inspection ◽  
Reference Sample ◽  
Ball Grid Array ◽  
Inspection System ◽  
Laser Ultrasonic ◽  
Fiber Array ◽  
Measurement Capability ◽  
Repeatability And Reproducibility ◽  
Ball Grid Array Packages

Abstract Laser ultrasonic inspection is a novel, noncontact, and nondestructive technique to evaluate the quality of solder interconnections in microelectronic packages. In this technique, identification of defects or failures in solder interconnections is performed by comparing the out-of-plane displacement signals, which are produced from the propagation of ultrasonic waves, from a known good reference sample and sample under test. The laboratory-scale dual-fiber array laser ultrasonic inspection system has successfully demonstrated identifying the defects and failures in the solder interconnections in advanced microelectronic packages such as chip-scale packages, plastic ball grid array packages, and flip-chip ball grid array packages. However, the success of any metrology system depends upon precise and accurate data to be useful in the microelectronic industry. This paper has demonstrated the measurement capability of the dual-fiber array laser ultrasonic inspection system using gage repeatability and reproducibility analysis. Industrial flip-chip ball grid array packages have been used for conducting experiments using the laser ultrasonic inspection system and the inspection data are used to perform repeatability and reproducibility analysis. Gage repeatability and reproducibility studies have also been used to choose a known good reference sample for comparing the samples under test.

Laser Ultrasonic Inspection of Solder Bumps in Flip Chip Packages Using Virtual Package Device as Reference

2010 ◽  
Author(s):  
I. Charles Ume ◽  
Jie Gong ◽  
Razid Ahmad ◽  
Abel Valdes
Keyword(s):  
Time Domain ◽  
Flip Chip ◽  
Electronic Device ◽  
Ultrasonic Inspection ◽  
Reference Method ◽  
Ultrasonic Waves ◽  
Quality Analysis ◽  
Inspection System ◽  
Solder Bumps

Flip chip package is widely used in the electronic device manufacturing industry. The top side of a flip chip device is manufactured with solder bumps. The device is then flipped on its top so that the solder bumps can be bonded to a substrate, forming the mechanical and electrical connection between the device and substrate. As a result, the solder bumps are sandwiched between the silicon die and the substrate, making them no longer visible for usual inspection. A novel solder joint inspection system capable of evaluating the quality of the hidden solder bumps on a flip chip package has been developed using laser ultrasound techniques. The system pulses a laser onto the top surface of a chip package to generate ultrasonic waves in the package and excite structural vibrations which can then be measured using an interferometer. Since defective solder bumps cause changes in the transient vibration response of a tested sample, quality of the tested sample can be assessed by correlating its vibration responses to that of a known good device. A limitation of this implementation is the necessity of a known-good reference chip package, which typically involves expensive testing using alternate methods. In this paper, the development of a method capable of generating a virtual reference chip package is presented. This method, called Hybrid Reference Method, uses a statistical approach to find which packages in a sample set are most similar and then averages their time domain signals to generate a virtual chip package, known as the Hybrid Reference Package. The signals associated with Hybrid Reference Package are then correlated with the time domain signals obtained from the packages under inspection to obtain a quality signature. Finally, defective and non-defective chip packages are separated by estimating a beta distribution that fits the quality signature histogram of the inspected packages and then determining a cutoff threshold for an acceptable quality signature. This method was applied to two types of flip chip packages where no pre-established known-good reference package was available. The results of this quality analysis were validated by comparison with electrical test and X-ray results.

Correlation Studies Between Laser Ultrasonic Inspection Data and Finite-element Modeling Results in Evaluation of Solder Joint Quality in Microelectronic Packages

2021 ◽  
Author(s):  
Vishnu Vardhan Busi Reddy ◽  
Saurabh Gupta ◽  
Jaimal Williamson ◽  
Suresh Sitaraman
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Ultrasonic Inspection ◽  
Ball Grid Array ◽  
Reliability Testing ◽  
Thermal Cycles ◽  
Laser Ultrasonic ◽  
Correlation Studies ◽  
Microelectronic Packages ◽  
Ball Grid Array Packages

Abstract Laser Ultrasonic Inspection (LUI) is a non-destructive and non-contact technique to evaluate the quality of solder ball interconnections in area-array microelectronic packages. Dual-Fiber Array Laser Ultrasonic Inspection System was demonstrated identifying defects and failures in chip-scale packages, ball grid array packages, and flip-chip ball grid array packages. The location and severity of the defects and failures in packages have been identified accurately using this system. Further, it is important to establish the correlation between LUI results and the severity of the failures for failure mode analysis, which will enable us to eliminate the need for destructive testing and allow the study of failure evolution in a given sample under continued reliability testing. This paper discusses correlation studies between experimental LUI results and finite-element simulation results from the flip-chip ball grid array packages subjected to thermal cycling reliability testing. The correlation equations will help in predicting the severity of the failures at a given number of thermal cycles based on LUI results. Furthermore, the life of the microelectronic packages can be predicted accurately from LUI results at a fewer number of thermal cycles.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

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