Network Loss Analysis of Low-Voltage Low-Power DC Microgrids for Rural Electrification

2020 ◽  
Author(s):  
Rabia Khan ◽  
Noel N. Schulz
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Rural Electrification ◽  
Dc Microgrids ◽  
Loss Analysis

Optimal Planning and Design of Low-Voltage Low-Power Solar DC Microgrids

2018 ◽  
Vol 33 (3) ◽  
pp. 2919-2928 ◽  
Author(s):  
Mashood Nasir ◽  
Saqib Iqbal ◽  
Hassan Abbas Khan
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Optimal Planning ◽  
Dc Microgrids ◽  
Planning And Design

scholarly journals Sustainable Rural Electrification Through Solar PV DC Microgrids—An Architecture-Based Assessment

Processes ◽  
2020 ◽  
Vol 8 (11) ◽  
pp. 1417
Author(s):  
Mashood Nasir ◽  
Saqib Iqbal ◽  
Hassan A. Khan ◽  
Juan C. Vasquez ◽  
Josep M. Guerrero
Keyword(s):  
Distributed Generation ◽  
Distributed Storage ◽  
Rural Electrification ◽  
Solar Photovoltaic ◽  
Power Electronic ◽  
Dc Microgrid ◽  
Dc Microgrids ◽  
Loss Analysis ◽  
Study Results ◽  
Central Storage

Solar photovoltaic (PV) direct current (DC) microgrids have gained significant popularity during the last decade for low cost and sustainable rural electrification. Various system architectures have been practically deployed, however, their assessment concerning system sizing, losses, and operational efficiency is not readily available in the literature. Therefore, in this research work, a mathematical framework for the comparative analysis of various architectures of solar photovoltaic-based DC microgrids for rural applications is presented. The compared architectures mainly include (a) central generation and central storage architecture, (b) central generation and distributed storage architecture, (c) distributed generation and central storage architecture, and (d) distributed generation and distributed storage architecture. Each architecture is evaluated for losses, including distribution losses and power electronic conversion losses, for typical power delivery from source end to the load end in the custom village settings. Newton–Raphson method modified for DC power flow was used for distribution loss analysis, while power electronic converter loss modeling along with the Matlab curve-fitting tool was used for the evaluation of power electronic losses. Based upon the loss analysis, a framework for DC microgrid components (PV and battery) sizing was presented and also applied to the various architectures under consideration. The case study results show that distributed generation and distributed storage architecture with typical usage diversity of 40% is the most feasible architecture from both system sizing and operational cost perspectives and is 13% more efficient from central generation and central storage architecture for a typical village of 40 houses. The presented framework and the analysis results will be useful in selecting an optimal DC microgrid architecture for future rural electrification implementations.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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