Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs

2010 ◽  
Vol 57 (11) ◽  
pp. 2864-2871 ◽  
Author(s):  
Tao Yu ◽  
Runsheng Wang ◽  
Ru Huang ◽  
Jiang Chen ◽  
Jing Zhuge ◽  
...  
2012 ◽  
Vol 629 ◽  
pp. 115-121
Author(s):  
Nor F. Za’bah ◽  
Kelvin S.K. Kwa ◽  
Anthony O’Neill

A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching has been developed using Silicon-on Insulator (SOI) as the starting substrate. The design of experiments for the optimization of the process flow especially on the orientation dependent etching using potassium hydroxide (KOH) and Tetra-Methyl Ammonium Hydroxide (TMAH) are presented in this paper. Based on the etching experiments using silicon substrates, KOH with added isopropyl alcohol (IPA) had shown to have a consistent etch rate with acceptable silicon surface roughness as compared with its other counterparts. The concern regarding the effect of line edge roughness (LER) as a result of optical lithography was highlighted and, therefore, the optimization of the patterning procedure was also discussed and presented.


2008 ◽  
Vol 47 (4) ◽  
pp. 2501-2505 ◽  
Author(s):  
Atsuko Yamaguchi ◽  
Daisuke Ryuzaki ◽  
Ken-ichi Takeda ◽  
Jiro Yamamoto ◽  
Hiroki Kawada ◽  
...  

Author(s):  
B. H. Hong ◽  
Y. C. Jung ◽  
S. W. Hwang ◽  
K. H. Cho ◽  
K. H. Yeo ◽  
...  

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