Numerical Simulation of N+ Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

2017 ◽  
Vol 64 (4) ◽  
pp. 1482-1488 ◽  
Author(s):  
Jaya Madan ◽  
Rishu Chaujar
Keyword(s):  
Numerical Simulation ◽  
Interface Trap ◽  
N Source ◽  
Tunnel Fet ◽  
Trap Charges

Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric

2017 ◽  
Vol 17 (1) ◽  
pp. 245-252 ◽  
Author(s):  
Pulimamidi Venkatesh ◽  
Kaushal Nigam ◽  
Sunil Pandey ◽  
Dheeraj Sharma ◽  
Pravin N. Kondekar
Keyword(s):  
Gate Dielectric ◽  
Interface Trap ◽  
Tunnel Fet ◽  
Trap Charges

Study of Interface Trap Charges in InAs Nanowire Tunnel FET

2019 ◽  
pp. 1165-1170
Author(s):  
Sankalp K. Singh ◽  
Ankur Gupta ◽  
Venkateshan Nagarajan ◽  
Deepak Anandan ◽  
Ramesh K. Kakkerla ◽  
...  
Keyword(s):  
Interface Trap ◽  
Tunnel Fet ◽  
Trap Charges

Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics

2018 ◽  
Vol 124 (7) ◽  
Author(s):  
Bandi Venkata Chandan ◽  
Kaushal Nigam ◽  
Dheeraj Sharma ◽  
Sunil Pandey
Keyword(s):  
Interface Trap ◽  
Tunnel Fet ◽  
Trap Charges
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