Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

Reliability analysis of cost-efficient CH3NH3PbI3 based dopingless tunnel FET

Electrostatically-doped TFETs (ED-TFETs) are amongst the most widely used cost-efficient steeper devices due to the use of charge-plasma technique and tunneling mechanism. However, the reliability analysis of ED-TFETs has considered as an important concern for the research community. Also, most studies have only focused on improving the performance of ED-TFETs such as dopingless (DL)-TFET in terms of on-current (ION), subthreshold swing (SS) and threshold voltage (Vth) rather than investigating the reliability issues. In this context, the aim of our work is to investigate the reliability analysis of our previously reported methyl-ammonium lead tri-iodide materials based DL-TFET (MAPbI3-DL-TFET). The influence of interface trap charges, shallow and deep defects on the electrical and analog performance of MAPbI3-DL-TFET has been analyzed using Silvaco ATLAS tool at room temperature. Extensive results carried out show that deep-level (Gaussian) defects impact the performance of the device prominently while the tail defects affect the device performance insignificantly. The present findings showed that the donor/acceptor effect the device in subthreshold regime considerably, while in superthreshold regime the impact of trap charges is marginal. In our view, these result emphasizes the reliability analysis of MAPbI3-DL-TFET for the very first time. We hope that our research will be useful and valuable for DL-TFET manufacturers.

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that positive trap having trap concentration of 1012/cm2 enhances the ION ~5.14x, SS by 44.75%, and various important RF/analog parameter such as transconductance (Gm) improves by a factor 5, device efficiency by 7.4% and intrinsic gain (Av) 80.4%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point show better performance in presence of positive and negative trap.