A High-Efficiency Multimode Li–Ion Battery Charger With Variable Current Source and Controlling Previous-Stage Supply Voltage

2009 ◽  
Vol 56 (7) ◽  
pp. 2469-2478 ◽  
Author(s):  
Jiann-Jong Chen ◽  
Fong-Cheng Yang ◽  
Chien-Chih Lai ◽  
Yuh-Shyan Hwang ◽  
Ren-Guey Lee
Author(s):  
Mustapha El Alaoui ◽  
Karim El Khadiri ◽  
Rachid El Alami ◽  
Ahmed Tahiri ◽  
Ahmed Lakhssassi ◽  
...  

A new Li-Ion battery charger interface (BCI) using pulse control (PC) technique is designed and analyzed in this paper. Thanks to the use of PC technique, the main standards of the Li-Ion battery charger, i.e. fast charge, small surface area and high efficiency, are achieved. The proposed charger achieves full charge in forty-one minutes passing by the constant current (CC) charging mode which also included the start-up and the constant voltage mode (CV) charging mode. It designed, simulated and layouted which occupies a small size area 0.1 mm2 by using Taiwan Semiconductor Manufacturing Company 180 nm complementary metal oxide semi-conductor technology (TSMC 180 nm CMOS) technology in Cadence Virtuoso software. The battery voltage VBAT varies between 2.9 V to 4.35 V and the maximum battery current IBAT is 2.1 A in CC charging mode, according to a maximum input voltage VIN equal 5 V. The maximum charging efficiency reaches 98%.


2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Youssef Ziadi ◽  
Hassan Qjidaa

This paper presents a high efficiency Li-ion battery LDO-based charger IC which adopted a three-mode control: trickle constant current, fast constant current, and constant voltage modes. The criteria of the proposed Li-ion battery charger, including high accuracy, high efficiency, and low size area, are of high importance. The simulation results provide the trickle current of 116 mA, maximum charging current of 448 mA, and charging voltage of 4.21 V at the power supply of 4.8–5 V, using 0.18 μm CMOS technology.


Author(s):  
Mustapha El Alaoui ◽  
Fouad Farah ◽  
Karim El khadiri ◽  
Ahmed Tahiri ◽  
Rachid El Alami ◽  
...  

In this work, the design and analysis of new Li-Ion battery charger interface using the switching-based technique is proposed for high efficiency, high speed charge and low area. The high efficiency, the lower size area and the fast charge are the more important norms of the proposed Li-Ion battery charger interface. The battery charging is completed passes to each charging mode: The first mode is the trickle charge mode (TC), the second mode is the constant current mode (CC) and the last mode is the constant voltage mode (CV), in thirty three minutes. The new Li-Ion battery charger interface is designed, simulated and layouted in Cadence software using TSCM 180 nm CMOS technology. With an input voltage V<sub>IN</sub> = 4.5 V, the output battery voltage (V<sub>BAT</sub>) may range from 2.7 V to 4.2 V and the maximum charging battery current (I<sub>BAT</sub>) is 1.7 A. The peak efficiency reaches 97% and the total area is only 0.03mm<sup>2</sup> .


Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1078
Author(s):  
Thi Thuy Pham ◽  
Dongmin Kim ◽  
Seo-Hyeong Jeong ◽  
Junghyup Lee ◽  
Donggu Im

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.


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