The Use of Photoinjection to Determine Oxide Charge Distributions and Interface Properties in MOS Structures-Invited Paper

1970 ◽  
Vol 17 (6) ◽  
pp. 41-46 ◽  
Author(s):  
R. J. Powell
2009 ◽  
Vol 311 (7) ◽  
pp. 1950-1953 ◽  
Author(s):  
S. Oktyabrsky ◽  
V. Tokranov ◽  
S. Koveshnikov ◽  
M. Yakimov ◽  
R. Kambhampati ◽  
...  

2005 ◽  
Vol 49 (7) ◽  
pp. 1223-1227 ◽  
Author(s):  
B.L. Yang ◽  
L.M. Lin ◽  
H.B. Lo ◽  
P.T. Lai

2004 ◽  
Vol 445-446 ◽  
pp. 144-146
Author(s):  
Masaki Maekawa ◽  
Atsuo Kawasuso ◽  
Masahito Yoshikawa ◽  
Ayahiko Ichimiya

1994 ◽  
Vol 338 ◽  
Author(s):  
R. Nachman ◽  
F. Cerrina

ABSTRACTIn this paper we address the degradation of oxide reliability after annealing the phosphorusdoped polysilicon of MOS structures. The oxide reliability was studied in terms of X-ray radiation sensitivity as well as breakdown characteristics.We found that annealing the polysilicon increased the radiation sensitivity of the gate oxide. We believe that this increase is a result of the phosphorus out-diffusion from the polysilicon into the oxide and a result of the creation of phosphorus related traps in the oxide bulk. We also found that the oxide charge to breakdown (Qbd) degradation correlates well with the density of the phosphorus in the oxide.


2006 ◽  
Vol 527-529 ◽  
pp. 987-990 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
H. Kawano ◽  
Masato Noborio ◽  
Jun Suda ◽  
Hiroyuki Matsunami

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.


Shinku ◽  
1967 ◽  
Vol 10 (12) ◽  
pp. 429-436
Author(s):  
Toyoki TAKEMOTO ◽  
Takashi ISHIHARA ◽  
Yasuaki TERUI ◽  
Kenji AKIYAMA

2019 ◽  
Vol 58 (7) ◽  
pp. 078001
Author(s):  
Koji Ito ◽  
Takuma Kobayashi ◽  
Tsunenobu Kimoto

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