scholarly journals Interface Properties of MOS Structures Prepared by Reactive Sputtering

Shinku ◽  
1967 ◽  
Vol 10 (12) ◽  
pp. 429-436
Author(s):  
Toyoki TAKEMOTO ◽  
Takashi ISHIHARA ◽  
Yasuaki TERUI ◽  
Kenji AKIYAMA
Keyword(s):  
Reactive Sputtering ◽  
Interface Properties ◽  
Mos Structures

Interface properties of MBE-grown MOS structures with InGaAs/InAlAs buried channel and in-situ high-k oxide

2009 ◽  
Vol 311 (7) ◽  
pp. 1950-1953 ◽  
Author(s):  
S. Oktyabrsky ◽  
V. Tokranov ◽  
S. Koveshnikov ◽  
M. Yakimov ◽  
R. Kambhampati ◽  
...  
Keyword(s):  
Interface Properties ◽  
Buried Channel ◽  
High K ◽  
Mos Structures

Interface Properties of 4H-SiC MOS Structures Studied by a Slow Positron Beam

2004 ◽  
Vol 445-446 ◽  
pp. 144-146
Author(s):  
Masaki Maekawa ◽  
Atsuo Kawasuso ◽  
Masahito Yoshikawa ◽  
Ayahiko Ichimiya
Keyword(s):  
Positron Beam ◽  
Interface Properties ◽  
Slow Positron ◽  
Mos Structures

Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N2O Annealing

2006 ◽  
Vol 527-529 ◽  
pp. 987-990 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
H. Kawano ◽  
Masato Noborio ◽  
Jun Suda ◽  
Hiroyuki Matsunami
Keyword(s):  
Breakdown Strength ◽  
Oxide Thickness ◽  
Interface State ◽  
State Density ◽  
Interface Properties ◽  
Gate Oxides ◽  
Channel Mobility ◽  
Oxide Deposition ◽  
Mos Structures

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.

scholarly journals Influence of vacuum annealing on interface properties of SiC (0001) MOS structures

2019 ◽  
Vol 58 (7) ◽  
pp. 078001
Author(s):  
Koji Ito ◽  
Takuma Kobayashi ◽  
Tsunenobu Kimoto
Keyword(s):  
Vacuum Annealing ◽  
Interface Properties ◽  
Mos Structures

Investigation of Deep Interface Traps in Very-Thin Oxide/Si Structures Prepared at Low Temperatures Using Chemical Solutions

2009 ◽  
Vol 609 ◽  
pp. 123-127
Author(s):  
Jaroslav Rusnák ◽  
Michal Ružinský ◽  
Kentaro Imamura ◽  
Taketoshi Matsumoto ◽  
Miloslav Štefečka ◽  
...  
Keyword(s):  
Low Temperatures ◽  
Low Voltage ◽  
Deep Level ◽  
Interface Properties ◽  
Voltage Step ◽  
Chemical Solutions ◽  
Thin Oxide ◽  
Transient Spectroscopy ◽  
Labview Platform ◽  
Mos Structures

An advanced equipment for the charge version of deep level transient spectroscopy (Q-DLTS) and C-V measurements with newly developed software on LabView platform is presented. The ability to record several Q-DLTS behaviors with different rate windows simultaneously is the most important property of the equipment. Q-DLTS with excitation of the MOS structures by low-voltage step and time domain C-V measurements were used to determine interface properties. The contribution presents mainly results obtained on very-thin oxide/n-type crystalline Si structures prepared by oxidation at very low temperatures in nitric acid solutions with various concentrations.

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