An Integrated Circuit Analyzer-Counter-Ratemeter and Position Device for Nuclear Spectroscopy Studies

1974 ◽  
Vol 21 (1) ◽  
pp. 826-837 ◽  
Author(s):  
P. E. Thiess ◽  
T. A. Visel ◽  
P. A. Kwitkowski
1990 ◽  
Vol 30 (2) ◽  
pp. ii
Author(s):  
WayneR Jones ◽  
DanielJ Voss

1974 ◽  
Vol 117 (1) ◽  
pp. 213-219 ◽  
Author(s):  
H.E. Bosch ◽  
J. Davidson ◽  
M.A. Fariolli ◽  
V. Silbergleit

Author(s):  
R. M. Anderson

Aluminum-copper-silicon thin films have been considered as an interconnection metallurgy for integrated circuit applications. Various schemes have been proposed to incorporate small percent-ages of silicon into films that typically contain two to five percent copper. We undertook a study of the total effect of silicon on the aluminum copper film as revealed by transmission electron microscopy, scanning electron microscopy, x-ray diffraction and ion microprobe techniques as a function of the various deposition methods.X-ray investigations noted a change in solid solution concentration as a function of Si content before and after heat-treatment. The amount of solid solution in the Al increased with heat-treatment for films with ≥2% silicon and decreased for films <2% silicon.


Author(s):  
Kemining W. Yeh ◽  
Richard S. Muller ◽  
Wei-Kuo Wu ◽  
Jack Washburn

Considerable and continuing interest has been shown in the thin film transducer fabrication for surface acoustic waves (SAW) in the past few years. Due to the high degree of miniaturization, compatibility with silicon integrated circuit technology, simplicity and ease of design, this new technology has played an important role in the design of new devices for communications and signal processing. Among the commonly used piezoelectric thin films, ZnO generally yields superior electromechanical properties and is expected to play a leading role in the development of SAW devices.


Author(s):  
S. Khadpe ◽  
R. Faryniak

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.


Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.


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