scholarly journals Scalable Digital CMOS Comparator Using a Parallel Prefix Tree

2013 ◽  
Vol 21 (11) ◽  
pp. 1989-1998 ◽  
Author(s):  
Saleh Abdel-Hafeez ◽  
Ann Gordon-Ross ◽  
Behrooz Parhami
2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 


2010 ◽  
Vol 4 (4) ◽  
pp. 306-316
Author(s):  
F. Liu ◽  
Q. Tan ◽  
O. Ait Mohamed ◽  
M. Gu ◽  
G. Chen ◽  
...  

2016 ◽  
Vol 833 ◽  
pp. 149-156
Author(s):  
L. Gurusamy ◽  
Muhammad Kashif ◽  
Norhuzaimin Julai

This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction in comparison of the traditional Carry Look-Ahead Adder (CLA).


Author(s):  
K.R. Shankarkumar ◽  
Gokul Kumar

: Filtering is an important step in the field of image processing to suppress the required parts or to remove any artifacts present in it. There are different types of filters like low pass, high pass, Band pass, IIR, FIR and adaptive filtering etc.., in these filters adaptive filters is an important filter because it is used to remove the noisy signal and images. Least Mean Square filter is a type of an adaptive filtering which is used to remove the noises present in the medical images. The working of LMS is based on the minimization of the difference between the error images using a closed loop feedback. Therefore presented technique called as Q-CSKA. Here the CSKA performs its operation in stages which is based on the nucleus stage. In the traditional CSKA the nucleus stage is depend on the parallel prefix adder in this work it is replaced by the QCA adder. The QCA adder utilizes the less area compared to PPA and it can be realized in Nanometer range also. For multiplexers, And OR Invert, OR and Invert logic is used to reduce the area and delay. Due to these advantages of the QCA, AOI-OAI logic the proposed method outperformed the LMS implementation in area, power, and accuracy and delay, this based five type image noise of medical pictures related to the best technique is out comes. It helps to medicinal practitioner to resolve the symptoms of patient with ease.


Author(s):  
Andrzej Handkiewicz ◽  
Mariusz Naumowicz

AbstractThe paper presents a method of optimizing frequency characteristics of filter banks in terms of their implementation in digital CMOS technologies in nanoscale. Usability of such filters is demonstrated by frequency-interleaved (FI) analog-to-digital converters (ADC). An analysis filter present in these converters was designed in switched-current technique. However, due to huge technological pitch of standard digital CMOS process in nanoscale, its characteristics substantially deviate from the required ones. NANO-studio environment presented in the paper allows adjustment, with transistor channel sizes as optimization parameters. The same environment is used at designing a digital synthesis filter, whereas optimization parameters are input and output conductances, gyration transconductances and capacitances of a prototype circuit. Transition between analog s and digital z domains is done by means of bilinear transformation. Assuming a lossless gyrator-capacitor (gC) multiport network as a prototype circuit, both for analysis and synthesis filter banks in FI ADC, is an implementation of the strategy to design filters with low sensitivity to parameter changes. An additional advantage is designing the synthesis filter as stable infinite impulse response (IIR) instead of commonly used finite impulse response (FIR) filters. It provides several dozen-fold saving in the number of applied multipliers.. The analysis and synthesis filters in FI ADC are implemented as filter pairs. An additional example of three-filter bank demonstrates versatility of NANO-studio software.


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