A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS

2018 ◽  
Author(s):  
Ryosuke Noguchi ◽  
Kosuke Furuichi ◽  
Hiromu Uemura Toshiyuki Inoue ◽  
Akira Tsuchiya ◽  
Keiji Kishine ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Flip Flop

scholarly journals Analyse und Entwurf von hochbitratigen Clock-and-Data-Recovery Schaltungen in CMOS-Technologie

2007 ◽  
Vol 5 ◽  
pp. 215-219
Author(s):  
J.-K. Bremer ◽  
C. Zemko ◽  
J. Schmackers ◽  
W. Mathis
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Detection Method ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Phase Detector ◽  
Phase Detection ◽  
Flip Flop ◽  
Fast Switching ◽  
Nonlinear Phase

Abstract. In dieser Arbeit wird ein neuartiges Schaltungskonzept für die Realisierung eines Phasendetektors einer Clock-and-Data-Recovery Schaltung vorgestellt. Es handelt sich hierbei um eine nichtlineare Phasendetektorarchitektur, die nach dem Verfahren von Alexander arbeitet. Um die Funktionalität des Phasendetektors im Hochfrequenzbereich zu gewährleisten, wurden in dem Design sehr schnell schaltende HLO-Flip-Flops (high-speed latching operation flip-flop) verwendet. Ein wesentliches Entwurfsziel war die Begrenzung des selbstgenerierten Jitters des Phasendetektors. Der Schaltungsentwurf wurde mit der Simulationsumgebung Cadence Spectre durchgeführt und die Funktionalität der Schaltung im GHz-Bereich anhand von ausgewählten Simulationen verifiziert. This paper presents a novel realization concept for Clock-and-Data-Recovery circuits. Our Design uses a nonlinear phase detector architecture, which is based on the Alexander phase detection method. In order to ensure circuit functionality in the RF region, we use very fast switching HLO-Flip-Flops (high-speed latching operation flip-flop) in our design. The primal goal in our design was the minimization of self induced jitter of the phase detector. The accuracy of our circuit design and the functionality in the GHz regime is confirmed by various circuit simulations executed with the SPECTRE Simulator.

scholarly journals A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 780
Author(s):  
Matteo D’Addato ◽  
Alessia M. Elgani ◽  
Luca Perilli ◽  
Eleonora Franchi Scarselli ◽  
Antonio Gnudi ◽  
...  
Keyword(s):  
Data Streams ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Rf Power ◽  
Input Matching ◽  
Analog Front End ◽  
Frequency Mismatch ◽  
Free Running ◽  
Frequency Calibration ◽  
Total Sensitivity

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

Design of high-speed burst mode clock and data recovery IC for passive optical network

2005 ◽  
Author(s):  
Minhui Yan ◽  
Xiaobin Hong ◽  
Wei-Ping Huang ◽  
Jin Hong
Keyword(s):  
High Speed ◽  
Optical Network ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Passive Optical Network ◽  
Burst Mode

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

An all-digital semi-blind clock and data recovery system

2015 ◽  
Vol 46 (4) ◽  
pp. 273-284
Author(s):  
Mina Abdallah ◽  
Ahmed Eladawy ◽  
Ahmed Mohieldin
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Recovery System
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