A Novel Deep Trench Isolation Featuring Airgaps for a High-Speed 0.13μm SiGe:C BiCMOS Technology

2006 ◽  
Author(s):  
L.j. Choi ◽  
X.p. Shi ◽  
R. Loo ◽  
S. Vanhaelemeersch ◽  
S. Decoutere ◽  
...  
Keyword(s):  
High Speed ◽  
Deep Trench ◽  
Bicmos Technology ◽  
Trench Isolation

Introduction of Airgap Deeptrench Isolation in STI Module for High Speed SiGe : C BiCMOS Technology

2006 ◽  
Vol 913 ◽  
Author(s):  
Eddy Kunnen ◽  
Li Jen Choi ◽  
Stefaan Van Huylenbroeck ◽  
Andreas Piontec ◽  
Frank Vleugels ◽  
...  
Keyword(s):  
High Speed ◽  
Substantial Reduction ◽  
Capacitive Coupling ◽  
Deep Trench ◽  
Available Bandwidth ◽  
A Value ◽  
Bicmos Technology ◽  
Trench Isolation ◽  
Order Of Magnitude ◽  
The Impact

AbstractThe impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.

High-speed latchup-free 0.5-µm-channel CMOS using self-aligned TiSi2and deep-trench isolation technologies

1983 ◽  
Author(s):  
T. Yamaguchi ◽  
S. Morimoto ◽  
G.H. Kawamoto ◽  
H.K. Park ◽  
G.C. Eiden
Keyword(s):  
High Speed ◽  
Deep Trench ◽  
Trench Isolation

Formation of defects in implanted hipox-structures

1992 ◽  
Vol 50 (2) ◽  
pp. 1406-1407
Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan
Keyword(s):  
High Pressure ◽  
Cross Section ◽  
Semiconductor Devices ◽  
Silicon Substrates ◽  
Processing Conditions ◽  
Pressure Oxidation ◽  
Deep Trench ◽  
Local Oxidation ◽  
Trench Isolation ◽  
And Behavior

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.

20-μm deep trench isolation process characterization for linear bipolar ICs

2001 ◽  
Author(s):  
Terry Dyer ◽  
Ian J. Doohan ◽  
Martin Fallon ◽  
Dave McAlpine ◽  
Adam Aitkenhead ◽  
...  
Keyword(s):  
Deep Trench ◽  
Process Characterization ◽  
Trench Isolation
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