Low power ASIC design for infrared sensor network inside ARIANE 5 vehicle equipment bay

Author(s):  
Hendra Kesuma ◽  
Sebastian Schmale ◽  
Steffen Paul ◽  
Johannes Sebald
Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 3128
Author(s):  
Thomas Ameloot ◽  
Patrick Van Torre ◽  
Hendrik Rogier

When aiming for the wider deployment of low-power sensor networks, the use of sub-GHz frequency bands shows a lot of promise in terms of robustness and minimal power consumption. Yet, when deploying such sensor networks over larger areas, the link quality can be impacted by a host of factors. Therefore, this contribution demonstrates the performance of several links in a real-world, research-oriented sensor network deployed in a (sub)urban environment. Several link characteristics are presented and analysed, exposing frequent signal deterioration and, more rarely, signal strength enhancement along certain long-distance wireless links. A connection is made between received power levels and seasonal weather changes and events. The irregular link performance presented in this paper is found to be genuinely disruptive when pushing sensor-networks to their limits in terms of range and power use. This work aims to give an indication of the severity of these effects in order to enable the design of truly reliable sensor networks.


2018 ◽  
Vol 12 (3) ◽  
pp. 2385-2394 ◽  
Author(s):  
Pei-Yih Ting ◽  
Jia-Lun Tsai ◽  
Tzong-Sun Wu

Author(s):  
Jukka Suhonen ◽  
Mikko Kohvakka ◽  
Ville Kaseva ◽  
Timo D. Hämäläinen ◽  
Marko Hännikäinen

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3884 ◽  
Author(s):  
Hongxian Tian ◽  
Mary Weitnauer ◽  
Gedeon Nyengele

We study the placement of gateways in a low-power wide-area sensor network, when the gateways perform interference cancellation and when the model of the residual error of interference cancellation is proportional to the power of the packet being canceled. For the case of two sensor nodes sending packets that collide, by which we mean overlap in time, we deduce a symmetric two-crescent region wherein a gateway can decode both collided packets. For a large network of many sensors and multiple gateways, we propose two greedy algorithms to optimize the locations of the gateways. Simulation results show that the gateway placements by our algorithms achieve lower average contention, which means higher packet delivery ratio in the same conditions, than when gateways are naively placed, for several area distributions of sensors.


VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.


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