Failure Estimation of Semiconductor Chip During Wire Bonding Process

1999 ◽  
Vol 121 (2) ◽  
pp. 85-91 ◽  
Author(s):  
T. Ikeda ◽  
N. Miyazaki ◽  
K. Kudo ◽  
K. Arita ◽  
H. Yakiyama

Wire bonding, a process of the connection between a semiconductor chip and a lead frame by a thin metal wire, is one of the important processes of electronic packaging. This paper presents failure estimation of a silicon chip and a GaAS chip during a gold wire bonding process. The gold wire bonding process is carried out by pressing a gold ball made at a tip of the gold wire on a semiconductor chip and vibrating it by ultrasonic. High contact pressure is useful for shortening the process cycle, but it sometimes causes failure of the semiconductor chip. Elastic-plastic large deformation contact analyses are performed and the distributions of the stresses in these semiconductor chips are investigated. The possibility of failure of a semiconductor chip under usual wire bonding pressure is pointed out only for a GaAs chip.

2016 ◽  
Vol 857 ◽  
pp. 31-35
Author(s):  
Wan Yusmawati Wan Yusoff ◽  
Azman Jalar ◽  
Norinsan Kamil Othman ◽  
Irman Abdul Rahman

The effect of high temperature storage of gold ball bonds towards micromechanical properties has been investigated. Gold wire from thermosonic wire bonding exposed to high temperature storage at 150 °C for 10, 100 and 1000 hours. The nanoindentation test was used in order to evaluate the high temperature storage effect on wire bonding in more details and localized. Prior to nanoindentation test, the specimens were cross-sectioned diagonally. The constant load nanoindentation was performed at the center of gold ball bond to investigate the hardness and reduced modulus. The load-depth curve of nanoindentation for the high temperature storage gold wire has apparent the discontinuity during loading compared to as-received gold wire. The hardness value increased after subjected to high temperature storage. However, the hardness decreased when the storage period is extended. The decreasing in the hardness value may due to the grain size of Au metal which recrystallized after subjected to high temperature storage. The results obtained from nanoindentation is important in assessing the high temperature storage of wire bonding.


2013 ◽  
Vol 804 ◽  
pp. 151-157 ◽  
Author(s):  
Hao Wen Hsueh ◽  
Fei Yi Hung ◽  
Truan Sheng Lui

Sliver wire was the novel material to replaced gold wire in wire bonding process, and rare earth element was often added to improve the properties of silver wires. The annealing effect (at 225°C~275°C for 30min) on the tensile mechanical properties of silver wires with φ=20μm was investigated. In addition, the microstructural characteristics and the mechanical properties before and after an electric flame-off (EFO) process were also studied. Free-air ball (FAB) of 85μm diameter from 20μm diameter pure silver wire was too huge for bonding process, otherwise the silver wire was added 0.05 wt.% lanthanum to form Ag-La alloy wire to reduce the diameter of FAB. FAB of Ag-La alloy wire with a 55μm diameter, and can avoid short-circuited. In addition, microstructures, tensile properties and the micro-hardness of Ag-La alloy wires indicated that the best annealing temperature was 425 °C.


2013 ◽  
Vol 275-277 ◽  
pp. 1925-1928
Author(s):  
Chun Yu Wang ◽  
Qing Wang ◽  
Han Zhu Li ◽  
Xiao Zhi Ji ◽  
Zhi Long Kang

Keywords: Electroless plating Ni, CeO2, Micro-connection pad, Wire bonding Abstract. It is Ni/CeO2 coatings that have been prepared on SiC/Al composites surfaces (electroless plating Ni and depositing CeO2 conversion coatings). It is employed to wire bonding process as a new micro-connection pad in this paper. During bonding process, ultrasonic time, ultrasonic power, bonding pressure, etc. have been investigated. The optimized parameters are obtained with the best bonding properties.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000638-000649 ◽  
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
John Foley ◽  
Ivy Qin

During the past two years copper wire bonding has entered high volume manufacturing at a number of leading edge OSATs and IDMs. Usage of copper wire has achieved 20% market share and is expected to exceed 50% within three years. Products spanning the range from low pin count devices with relatively large wire diameter to FPGA's with nearly one thousand wires at 20 μm or even 18 μm wire are now using copper wire. This paper will discuss the requirements for developing a robust copper wire bonding process and then moving it to high volume manufacturing. Process optimization begins with the selection of the appropriate wire diameter, ball diameter, bonding tool and bonding process type. These are functions not only of the bond pad opening, but also of the pad aluminum thickness and relative sensitivity of the pad to damage. Proper optimization depends on the availability of new and modified bond quality metrologies, such as extensive reliance on cross-sectioning and intermetallic coverage measurements. The bonding window of a copper wire bonding process is defined in substantially new terms compared to optimization in gold wire bonding. Once an optimized process has been developed in the lab on a single bonder, it needs to be verified. Copper wire bond processes are much less forgiving with respect to the acceptable variability on the manufacturing floor. To ensure that the process is stable, a low volume pre-manufacturing test is highly recommended. This not only makes sure that the process is stable across multiple bonders, but also ensures the adequacies of manufacturing controls, incoming materials quality and sufficient equipment calibration and maintenance procedures.


2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Xiuqian Wu ◽  
Dehong Ye ◽  
Hanmin Zhang ◽  
Li Song ◽  
Liping Guo

Purpose This paper aims to investigate the root causes of and implement the improvements for the inter layer dielectric (ILD) crack for LQFP C90FG (CMOS90 Floating Gate) wafer technology devices in copper wire bonding process. Design/methodology/approach Failure analysis was conducted including cratering, scanning electron microscopy inspection and focus ion beam cross-section analysis, which showed ILD crack. Root cause investigation of ILD crack rate sudden jumping was carried out with cause-and-effect analysis, which revealed the root cause is shallower lead frame down-set. ILD crack mechanism deep-dive on ILD crack due to shallower lead frame down-set, which revealed the mechanism is lead frame flag floating on heat insert. Further investigation and energy dispersive X-ray analysis found the Cu particles on heat insert is another factor that can result in lead frame flag floating. Findings Lead frame flag floating on heat insert caused by shallower lead frame down-set or foreign matter on heat insert is a critical factor of ILD crack that has never been revealed before. Weak wafer structure strength caused by thinner wafer passivation1 thickness and sharp corner at Metal Trench (compared with the benchmarking fab) are other factors that can impact ILD crack. Originality/value For ILD crack improvement in copper wire bonding, besides the obvious factors such as wafer structure and wire bonding parameters, also should take other factors into consideration including lead frame flag floating on heat insert and heat insert maintenance.


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