PART I: BOND STRAIN AND DEFECTS AT Si-SiO2 AND DIELECTRIC INTERFACES IN HIGH-k GATE STACKS

2006 ◽  
Vol 16 (01) ◽  
pp. 241-261 ◽  
Author(s):  
GERALD LUCOVSKY

The performance and reliability of aggressively-scaled field effect transistors that include deposited high-k dielectrics and interfacial SiO 2 buffer layers are determined in large part by electronically-active defects and defect precursors at the Si - SiO 2, and internal SiO 2-high-k dielectric interfaces. A crucial aspect of reducing interfacial defects and defect precursors is associated with bond-strain driven bonding self-organizations that take place during high temperature annealing in inert ambients. These interfacial self-organizations, and intrinsic interface defects are addressed through an extension of bond constraint theory from bulk glasses to interfaces between non-crystalline SiO 2, and i) crystalline Si , and ii) non-crystalline and crystalline alternative gate dielectric materials.

2009 ◽  
Vol 1155 ◽  
Author(s):  
Xuhui Luo ◽  
Alex Demkov ◽  
Onise Sharia ◽  
Gennadi Bersuker

AbstractHafnium dioxide that belongs to a class of metal oxides with a high dielectric constant or high-k dielectrics has been recently introduced as a gate dielectric in field effect transistors. We report a theoretical study of structural and electronic properties of hafnia surface, and the electronic structure and band alignment at hafnia interfaces with metals, oxides and semiconductors that are crucial in gate stack engineering.


2001 ◽  
Vol 76-77 ◽  
pp. 19-22 ◽  
Author(s):  
J.J. Guan ◽  
Glenn W. Gale ◽  
G. Bersuker ◽  
M. Jackson ◽  
Howard R. Huff

2020 ◽  
Vol 9 (3) ◽  
pp. 943-949
Author(s):  
Ankita Dixit ◽  
Navneet Gupta

In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2. It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results


2002 ◽  
Vol 303 (1) ◽  
pp. 54-63 ◽  
Author(s):  
P.S. Lysaght ◽  
P.J. Chen ◽  
R. Bergmann ◽  
T. Messina ◽  
R.W. Murto ◽  
...  

1999 ◽  
Vol 567 ◽  
Author(s):  
G. Lucovsky ◽  
J.C. Phillips

ABSTRACTThis paper discusses chemical bonding effects at Si-dielectric interfaces that are important in the implementation of alternative gate dielectrics including: i) the character of interfacial bonds, either isovalent with bond and nuclear charge balanced as in Si-SiO2, or heterovalent, with an inherent mismatch between bond and nuclear charge, ii) mechanical bonding constraints related to the average number of bonds/atom, Nay, and iii) band offset energies that are reduced in transition metal oxides due to the d-state origins of the conduction band states. Applications are made to specific classes of dielectric materials including i) nitrides and oxide/nitride stacks and ii) alternative high-K gate materials.


AIP Advances ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 065229
Author(s):  
Yanxiao Sun ◽  
Gang Niu ◽  
Wei Ren ◽  
Jinyan Zhao ◽  
Yankun Wang ◽  
...  

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