A FPGA-BASED PARAMETRIZABLE SYSTEM FOR HIGH-RESOLUTION FREQUENCY-DOMAIN IMAGE FILTERING

2005 ◽  
Vol 14 (05) ◽  
pp. 895-921
Author(s):  
ISA SERVAN UZUN ◽  
ABBES AMIRA
Keyword(s):  
Image Processing ◽  
Frequency Domain ◽  
High Performance ◽  
Fourier Transforms ◽  
Processing System ◽  
Image Filtering ◽  
Input Image ◽  
Frame Rate ◽  
Detailed Knowledge ◽  
Image Size

Signal and image processing applications require high computational power with the ability to experiment different algorithms involving matrix transforms. Reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed to obtain high performance at an economical price. However, the users must program FPGAs at a very low level and must have a detailed knowledge of the architecture of the device being used. In trying to reconcile the dual requirements of high performance and the ease of development, this paper reports the design and realization of the Fast Fourier Transforms (FFTs) using a FPGA-based environment, which enables system designer to meet different system requirements (i.e., chip area, speed, memory, etc.) for a range of signal processing and imaging applications. The use of the proposed environment has been proven by the developing a high-level FPGA-based parametrizable image processing system for frequency-domain filtering application. The system achieves real-time image filtering performance exceeding those of currently available solutions by an order of magnitude in frame rate and input image size.

scholarly journals Impact of Input Data on Intelligence Partitioning Decisions for IoT Smart Camera Nodes

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1898
Author(s):  
Isaac Sánchez Leal ◽  
Irida Shallari ◽  
Silvia Krug ◽  
Axel Jantsch ◽  
Mattias O’Nils
Keyword(s):  
Image Processing ◽  
Internet Of Things ◽  
Input Data ◽  
Processing System ◽  
Input Image ◽  
Smart Camera ◽  
Image Size ◽  
Depth Analysis ◽  
Camera Nodes ◽  
Node Energy

Image processing systems exploit image information for a purpose determined by the application at hand. The implementation of image processing systems in an Internet of Things (IoT) context is a challenge due to the amount of data in an image processing system, which affects the three main node constraints: memory, latency and energy. One method to address these challenges is the partitioning of tasks between the IoT node and a server. In this work, we present an in-depth analysis of how the input image size and its content within the conventional image processing systems affect the decision on where tasks should be implemented, with respect to node energy and latency. We focus on explaining how the characteristics of the image are transferred through the system until finally influencing partition decisions. Our results show that the image size affects significantly the efficiency of the node offloading configurations. This is mainly due to the dominant cost of communication over processing as the image size increases. Furthermore, we observed that image content has limited effects in the node offloading analysis.

Massive Image Treatment System Based on Cloud Computing Platform

2014 ◽  
Vol 687-691 ◽  
pp. 3733-3737
Author(s):  
Dan Wu ◽  
Ming Quan Zhou ◽  
Rong Fang Bie
Keyword(s):  
Image Processing ◽  
Cloud Computing ◽  
High Performance ◽  
Large Scale ◽  
Processing System ◽  
Virtual Space ◽  
Image Processing System ◽  
Computing Platform ◽  
Simulation Calculation ◽  
Computer Resources

Massive image processing technology requires high requirements of processor and memory, and it needs to adopt high performance of processor and the large capacity memory. While the single or single core processing and traditional memory can’t satisfy the need of image processing. This paper introduces the cloud computing function into the massive image processing system. Through the cloud computing function it expands the virtual space of the system, saves computer resources and improves the efficiency of image processing. The system processor uses multi-core DSP parallel processor, and develops visualization parameter setting window and output results using VC software settings. Through simulation calculation we get the image processing speed curve and the system image adaptive curve. It provides the technical reference for the design of large-scale image processing system.

scholarly journals A portable smartphone-based laryngoscope system for high-speed vocal cord imaging of patients with throat disorders (Preprint)

2020 ◽  
Author(s):  
Jun Ki Kim ◽  
Youngkyu Kim ◽  
Jungmin Oh ◽  
Seung-Ho Choi ◽  
Ahra Jung ◽  
...  
Keyword(s):  
Image Processing ◽  
Vocal Cord ◽  
High Speed ◽  
High Performance ◽  
Vocal Folds ◽  
Frame Rate ◽  
Endoscopic Imaging ◽  
High Speed Imaging ◽  
Underdeveloped Countries ◽  
Longitudinal Edge

BACKGROUND Recently, high-speed digital imaging (HSDI), especially HSD endoscopic imaging is being routinely used for the diagnosis of vocal fold disorders. However, high-speed digital endoscopic imaging devices are usually large and costly, which limits access by patients in underdeveloped countries and in regions with inadequate medical infrastructure. Modern smartphones have sufficient functionality to process the complex calculations that are required for processing high-resolution images and videos with a high frame rate. Recently, several attempts have been made to integrate medical endoscopes with smartphones to make them more accessible to underdeveloped countries. OBJECTIVE To develop a smartphone adaptor for endoscopes to reduce the cost of devices, and to demonstrate the possibility of high-speed vocal cord imaging using the high-speed imaging functions of a high-performance smartphone camera. METHODS A customized smartphone adaptor was designed for clinical endoscopy using selective laser melting (SLM)-based 3D printing. Existing laryngoscope was attached to the smartphone adaptor to acquire high-speed vocal cord endoscopic images. Only existing basic functions of the smartphone camera were used for HSDI of the vocal folds. For image processing, segmented glottal areas were calculated from whole HSDI frames, and characteristics such as volume, shape and longitudinal edge length were analyzed. RESULTS High-speed digital smartphone imaging with the smartphone-endoscope adaptor could achieve 940 frames per second, and was used to image the vocal folds of five volunteers. The image processing and analytics demonstrated successful calculation of relevant diagnostic variables from the acquired images. CONCLUSIONS A smartphone-based HSDI endoscope system can function as a point-of-care clinical diagnostic device. Furthermore, this system is suitable for use as an accessible diagnostic method in underdeveloped areas with inadequate medical service infrastructure.

scholarly journals Metric Embedding Learning on Multi-Directional Projections

Algorithms ◽  
2020 ◽  
Vol 13 (6) ◽  
pp. 133 ◽  
Author(s):  
Gábor Kertész
Keyword(s):  
Feature Extraction ◽  
High Performance ◽  
Classification Performance ◽  
Difficult Problem ◽  
Input Image ◽  
Image Size ◽  
Matching Problems ◽  
Low Efficiency ◽  
Multi Class Classification ◽  
Directional Image

Image based instance recognition is a difficult problem, in some cases even for the human eye. While latest developments in computer vision—mostly driven by deep learning—have shown that high performance models for classification or categorization can be engineered, the problem of discriminating similar objects with a low number of samples remain challenging. Advances from multi-class classification are applied for object matching problems, as the feature extraction techniques are the same; nature-inspired multi-layered convolutional nets learn the representations, and the output of such a model maps them to a multidimensional encoding space. A metric based loss brings same instance embeddings close to each other. While these solutions achieve high classification performance, low efficiency is caused by memory cost of high parameter number, which is in a relationship with input image size. Upon shrinking the input, the model requires less trainable parameters, while performance decreases. This drawback is tackled by using compressed feature extraction, e.g., projections. In this paper, a multi-directional image projection transformation with fixed vector lengths (MDIPFL) is applied for one-shot recognition tasks, trained on Siamese and Triplet architectures. Results show, that MDIPFL based approach achieves decent performance, despite of the significantly lower number of parameters.

scholarly journals Processing of high-speed videos of shock wave boundary layer interactions

2020 ◽  
Author(s):  
Samee Maharjan ◽  
Dag Bjerketvedt ◽  
Ola Marius Lysaker
Keyword(s):  
Boundary Layer ◽  
Shock Wave ◽  
Image Processing ◽  
High Speed ◽  
Frame Rate ◽  
Image Size ◽  
Pressure Transducers ◽  
Reflected Shock ◽  
Shock Position ◽  
Wave Boundary

Abstract This paper presents a framework for processing high-speed videos recorded during gas experiments in a shock tube. The main objective is to study boundary layer interactions of reflected shock waves in an automated way, based on image processing. The shock wave propagation was recorded at a frame rate of 500,000 frames per second with a Kirana high-speed camera. Each high-speed video consists of 180 frames, with image size [$$768 \times 924$$ 768 × 924 ] pixels. An image processing framework was designed to track the wave front in each image and thereby estimate: (a) the shock position; (b) position of triple point; and (c) shock angle. The estimated shock position and shock angle were then used as input for calculating the pressure exerted by the shock. To validate our results, the calculated pressure was compared with recordings from pressure transducers. With the proposed framework, we were able to identify and study shock wave properties that occurred within less than $$300\, \upmu \hbox {sec}$$ 300 μ sec and to track evolveness over a distance of 100 mm. Our findings show that processing of high-speed videos can enrich, and give detailed insight, to the observations in the shock experiments.

Real-Time Primary Image Processing

2013 ◽  
pp. 33-53
Author(s):  
Radu Dobrescu ◽  
Dan Popescu
Keyword(s):  
Image Processing ◽  
Real Time ◽  
Median Filter ◽  
Processing System ◽  
Input Image ◽  
Sensing Element ◽  
Software Configuration ◽  
Software Algorithms ◽  
Primary Image ◽  
High Level

Image processing operations have been classified into three main levels, namely low (primary), intermediate, and high. In order to combine speed and flexibility, an optimum hardware/software configuration is required. For multitask primary processing, a pipeline configuration is proposed. This structure, which is an interface between the sensing element (camera) and the main processing system, achieves real time video signal preprocessing, during the image acquisition time. In order to form the working neighborhoods, the input image signal is delayed (two lines and three pixels). Thus, locally 3×3 type processing modules are created. A successive comparison median filter and a logical filter for edge detection are implemented for a pipeline configuration. On the other hand, for low level, intermediate, and high level operations, software algorithms on parallel platforms are proposed. Finally, a case study of lines detection using directional filter discusses the performance dependency on number of processors.

scholarly journals Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

2018 ◽  
Vol 2018 ◽  
pp. 1-17 ◽  
Author(s):  
Faisal Mahmood ◽  
Märt Toots ◽  
Lars-Göran Öfverstedt ◽  
Ulf Skoglund
Keyword(s):  
Energy Consumption ◽  
Biomedical Applications ◽  
High Performance ◽  
Fourier Transforms ◽  
External Memory ◽  
Image Size ◽  
Artifact Removal ◽  
Spectral Leakage ◽  
Discrete Fourier Transforms ◽  
Intermediate Storage

Two-dimensional discrete Fourier transform (DFT) is an extensively used and computationally intensive algorithm, with a plethora of applications. 2D images are, in general, nonperiodic but are assumed to be periodic while calculating their DFTs. This leads to cross-shaped artifacts in the frequency domain due to spectral leakage. These artifacts can have critical consequences if the DFTs are being used for further processing, specifically for biomedical applications. In this paper we present a novel FPGA-based solution to calculate 2D DFTs with simultaneous edge artifact removal for high-performance applications. Standard approaches for removing these artifacts, using apodization functions or mirroring, either involve removing critical frequencies or necessitate a surge in computation by significantly increasing the image size. We use a periodic plus smooth decomposition-based approach that was optimized to reduce DRAM access and to decrease 1D FFT invocations. 2D FFTs on FPGAs also suffer from the so-called “intermediate storage” or “memory wall” problem, which is due to limited on-chip memory, increasingly large image sizes, and strided column-wise external memory access. We propose a “tile-hopping” memory mapping scheme that significantly improves the bandwidth of the external memory for column-wise reads and can reduce the energy consumption up to 53%. We tested our proposed optimizations on a PXIe-based Xilinx Kintex 7 FPGA system communicating with a host PC, which gives us the advantage of further expanding the design for biomedical applications such as electron microscopy and tomography. We demonstrate that our proposed optimizations can lead to 2.8× reduced FPGA and DRAM energy consumption when calculating high-throughput 4096×4096 2D FFTs with simultaneous edge artifact removal. We also used our high-performance 2D FFT implementation to accelerate filtered back-projection for reconstructing tomographic data.

scholarly journals RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS

2017 ◽  
Vol 10 (13) ◽  
pp. 180
Author(s):  
Maheswari R ◽  
Pattabiraman V ◽  
Sharmila P
Keyword(s):  
Image Processing ◽  
Image Quality ◽  
Reconfigurable Computing ◽  
High Performance ◽  
Critical Path ◽  
Computational Cost ◽  
Parallel Execution ◽  
Soft Core ◽  
Frame Rate ◽  
Time Data

Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF (Reconfigurable Register File) with multiple core functionalities. This work aims at analyzing the functionality of the reconfigurable architecture, by illustrating the implementation of two different image processing operations such as image convolution and image quality improvement. The MAC (Multiply-Accumulate) unit of ROR1200 used to perform image convolution and execution unit with HPRC is used for image quality improvement.Result: With parallel execution in multi-core, the proposed processor improves image quality by doubling the frame rate up-to 60 fps (frames per second) with peak power consumption of 400mWatt. Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for portable embedded SIMD based applications which need high performance at reduced power consumptions

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