A high-precision interface for tunneling magnetoresistance sensors with 0.15 nT/√Hz resolution

The tunneling magnetoresistance (TMR) with high-resolution digital output is widely used in military and civil fields. In this work we proposed a low-noise read-out circuit and a four-order fully differential sigma-delta modulator for TMR sensors. In the read-out circuit, we used symmetrical cascade for good matching. We used correlated double sampling (CDS) technique to improve the conversion accuracy of the modulator. In switched capacitor circuits we used time-division multiplexing to suppress charge injection and clock feedthrough. The high-precision application specific integrated circuit (ASIC) chip was fabricated by a 0.35 [Formula: see text]m CMOS process from Shanghai Huahong foundry. The TMR sensor was placed in an environment of three-layer magnetic shielding for test. The active area of the ASIC is only about [Formula: see text]. At a sampling frequency of 20 kHz, the TMR magnetometer consumes 77 mW from a single 5 V supply; the sigma-delta modulator for TMR can achieve an average noise floor of −141 dBV. The magnetometer works at a full scale (FS) of [Formula: see text], it can achieve a nonlinearity of 0.2% FS and a resolution of 0.15 nT/Hz[Formula: see text] over a signal bandwidth.

Design of an Ultrasound Transceiver ASIC with a Switching-Artifact Reduction Technique for 3D Carotid Artery Imaging

This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmissions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136[Formula: see text]mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

A Self-Oscillating System to Measure the Conductivity and the Permittivity of Liquids within a Single Triangular Signal

We present a methodology and a circuit to extract liquid resistance and capacitance simultaneously from the same output signal using interdigitated sensing electrodes. The principle consists in the generation of a current square wave and its application to the sensor to create a triangular output voltage which contains both the conductivity and permittivity parameters in a single periodic segment. This concept extends the Triangular Waveform Voltage (TWV) signal generation technique and is implemented by a system which consists in a closed-loop current-controlled oscillator and only requires DC power to operate. The system interface is portable and only a small number of electrical components are used to generate the expected signal. Conductivities of saline NaCl and KCl solutions, being first calibrated by commercial equipment, are characterized by a system prototype. The results show excellent linearity and prove the repeatability of the measurements. Experiments on water-glycerol mixtures validate the proposed sensing approach to measure the permittivity and the conductivity simultaneously. We discussed and identified the sources of measurement errors as circuit parasitic capacitances, switching clock feedthrough, charge injection, bandwidth, and control-current quality.