UNIFICATION OF PR REGION FLOORPLANNING AND FINE-GRAINED PLACEMENT FOR DYNAMIC PARTIALLY RECONFIGURABLE FPGAS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350020 ◽  
Author(s):  
RUINING HE ◽  
GUOQIANG LIANG ◽  
YUCHUN MA ◽  
YU WANG ◽  
JINIAN BIAN
Keyword(s):  
Global Optimization ◽  
Design Method ◽  
Critical Path ◽  
Design Flow ◽  
Path Delay ◽  
Wire Length ◽  
Fine Grained ◽  
Effective Strategies ◽  
Optimization Framework ◽  
Current Design

Dynamic Partially Reconfiguration (DPR) designs provide additional benefits compared to traditional FPGA application. However, due to the lack of support from automatic design tools in current design flow, designers have to manually define the dimensions and positions of Partially Reconfigurable Regions (PR Regions). The following fine-grained placement for system modules is also limited because it takes the floorplanning result as a rigid region constraint. Therefore, the manual floorplanning is laborious and may lead to inferior fine-grained placement results. In this paper, we propose to integrate PR Region floorplanning with fine-grained placement to achieve the global optimization of the whole DPR system. Effective strategies for tuning PR Region floorplanning and apposite analytical evaluation models are customized for DPR designs to handle the co-optimization for both PR Regions and static region. Not only practical reconfiguration cost and specific reconfiguration constraints for DPR system are considered, but also the congestion estimation can be relaxed by our approach. Especially, we established a two-stage stochastic optimization framework which handles different objectives in different optimization stages so that automated floorplanning and global optimization can be achieved in reasonable time. Experimental results demonstrate that due to the flexibility benefit from the unification of PR Region floorplanning and fine-grained placement, our approach can improve 20.9% on critical path delay, 24% on reconfiguration delay, 12% on congestion, and 8.7% on wire length compared to current DPR design method.

scholarly journals Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters

2012 ◽  
Vol 2012 ◽  
pp. 1-19 ◽  
Author(s):  
Soumya Kondapalli ◽  
Arjuna Madanayake ◽  
Len Bruton
Keyword(s):  
Design Method ◽  
Critical Path ◽  
Temporal Frequency ◽  
Massively Parallel ◽  
Path Delay ◽  
Finite Precision ◽  
Vlsi Architectures ◽  
Look Ahead ◽  
Digital Arithmetic ◽  
Spatio Temporal

A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded forK-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metricsATandAT2. TheL2error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits.

scholarly journals ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1439 ◽  
Author(s):  
Rohit Agrawal ◽  
Kapil Ahuja ◽  
Chin Hau Hoo ◽  
Tuan Duy Anh Nguyen ◽  
Akash Kumar
Keyword(s):  
Gradient Method ◽  
Critical Path ◽  
Design Flow ◽  
Channel Width ◽  
Path Delay ◽  
Routing Metric ◽  
Fpga Design ◽  
Critical Path Delay ◽  
Field Programmable ◽  
Primal Dual

In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing process to achieve significant speed-ups (the resulting algorithm is termed as ParaLaR). However, this approach has certain weaknesses. Namely, the constraints violation by the solution and a standard routing metric could be improved. We address these two issues here. In this paper, we use the LP framework of ParaLaR and solve it using the primal–dual sub-gradient method that better exploits the problem properties. We also propose a better way to update the size of the step taken by this iterative algorithm. We call our algorithm as ParaLarPD. We perform experiments on a set of standard benchmarks, where we show that our algorithm outperforms not just ParaLaR but the standard existing algorithm VPR as well. We perform experiments with two different configurations. We achieve 20 % average improvement in the constraints violation and the standard metric of the minimum channel width (both of which are related) when compared with ParaLaR. When compared to VPR, we get average improvements of 28 % in the minimum channel width (there is no constraints violation in VPR). We obtain the same value for the total wire length as by ParaLaR, which is 49 % better on an average than that obtained by VPR. This is the original metric to be minimized, for which ParaLaR was proposed. Next, we look at the third and easily measurable metric of critical path delay. On an average, ParaLarPD gives 2 % larger critical path delay than ParaLaR and 3 % better than VPR. We achieve maximum relative speed-ups of up to seven times when running a parallel version of our algorithm using eight threads as compared to the sequential implementation. These speed-ups are similar to those as obtained by ParaLaR.

Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms

2020 ◽  
pp. 2150081
Author(s):  
P. Sudhanya ◽  
S. P. Joy Vasantha Rani
Keyword(s):  
Critical Path ◽  
Iterative Algorithms ◽  
Path Delay ◽  
Local Minima ◽  
Wire Length ◽  
Inertia Weight ◽  
Critical Path Delay ◽  
Field Programmable ◽  
Fpga Placement ◽  
Run Time

This paper introduces hybrid iterative algorithms that combine Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms for Field Programmable Gate Array (FPGA) placement by considering adaptive inertia weight and local minima avoidance. The algorithms target to optimize the wire-length of the nets, run time and critical path delay in the placement of logic blocks. Using the adaptive inertia weight parameter and local minima avoidance, the hybrid PSO-SA algorithm is modified to Time-varying PSO-SA (TPSO-SA) and Modified PSO-SA (MPSO-SA) algorithm, respectively. These different hybrid PSO-SA algorithms are checked for efficiency by comparing with the Versatile Place and Route (VPR) algorithm of the Verilog to Routing (VTR) tool using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The hybrid PSO-SA algorithms give 5–37% better results for wire-length cost and 20–58% reduction in runtime compared to the VPR placement algorithm on different benchmark circuits. Critical path delay is also taken into consideration.

A FAST AND EFFECTIVE TIMING-DRIVEN PLACEMENT TOOL FOR FPGAs

2008 ◽  
Vol 17 (04) ◽  
pp. 663-673 ◽  
Author(s):  
MOHAMMED A. S. KHALID ◽  
YONGHONG XU
Keyword(s):  
North Carolina ◽  
Critical Path ◽  
Linear Equations ◽  
Path Delay ◽  
Wire Length ◽  
High Quality ◽  
Dense Area ◽  
Indirect Measure ◽  
Equation Solving ◽  
Placement And Routing

In this paper, we present TQPF, a Timing-Driven Quadratic-based Placement Tool for FPGAs. Quadratic placement algorithms try to minimize total squared wire length by solving linear equations. The resulting placement tends to locate all cells near the center of the chip with a large amount of overlap. Also, since squared wire length is only an indirect measure of linear wire length, the resulting total wire length may not be minimized. We propose methods to alleviate the above two problems that give high-quality results while minimizing the total run time. We incorporate multiple iterations of equation-solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length. Experimental results using 20 Microelectronics Center of North Carolina (MCNC) benchmark circuits show that, on average, TQPF is approximately three times faster than the well-known Versatile Placement and Routing tool for FPGAs (VPR). The estimated total wire length, on average, is only 1.4% longer, and the critical path delay is 4.9% lower.

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

Factored axial compressive resistance of schifflerized angles

1991 ◽  
Vol 18 (6) ◽  
pp. 926-932 ◽  
Author(s):  
Seshu Madhava Rao Adluri ◽  
Murty K. S. Madugula
Keyword(s):  
Key Words ◽  
Design Method ◽  
Design Criteria ◽  
Design Practice ◽  
Buckling Mode ◽  
Flexural Buckling ◽  
Mode Of Failure ◽  
Current Design ◽  
Similarities And Differences ◽  
Compressive Resistance

The concept of schifflerization of 90° equal-leg angle is presented and its application in triangular-base latticed steel towers is explained. The similarities and differences between schifflerized angles and regular 90° angles are discussed. The current design practice for schifflerized angles is reviewed and its limitation is highlighted. A design method which includes the effect of the torsional-flexural buckling mode of failure is proposed. For ready use of designers, the factored axial compressive resistances of schifflerized angles are tabulated for both the present and proposed design methods. Key words: buckling, compressive resistance, design criteria, schifflerized angles, stability, standards, steel, struts, towers, guyed towers.

scholarly journals High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz Mir
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
High Efficiency ◽  
Critical Path ◽  
Fir Filters ◽  
Path Delay ◽  
Look Up Table ◽  
Improved Performance ◽  
Ip Cores ◽  
Low Efficiency

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

Researches on the Shear Deformation of Joints Domain of Beam-to-Column Connection of Light Steel Structure

2012 ◽  
Vol 256-259 ◽  
pp. 1004-1007
Author(s):  
Xi Bing Hu ◽  
Jian Hua Lu
Keyword(s):  
Finite Element Method ◽  
Shear Deformation ◽  
Design Method ◽  
Steel Structure ◽  
Structure Calculation ◽  
The Finite Element Method ◽  
Mechanics Performance ◽  
Current Design ◽  
Internal Forces ◽  
Complex Parts

The joint domain of beam-to-column connection is very complex parts under loading, which plays an important role in transferring internal forces in light steel structure, such as moment, shear, axial force and so on. Considering the influence of its shear deformation in the structure calculation can help us to reflect the actual mechanics performance and evaluate precisely practical bearing capacity of the structure. According to the actual characteristics of beam-to-column connection, the author established some models of its joint domain, and used the finite element method to analyze and calculate shear deformation of these models. Meanwhile, the author researched the influence of the changes of various parameters to its shear deformation, and provided beneficial suggestions for revising the current design method of light steel structure finally.

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