FPGA BASED OPC UA EMBEDDED INDUSTRIAL DATA SERVER IMPLEMENTATION

2013 ◽  
Vol 22 (08) ◽  
pp. 1350070 ◽  
Author(s):  
RAFAL CUPEK ◽  
ADAM ZIEBINSKI ◽  
MACIEJ FRANEK
Keyword(s):  
Embedded System ◽  
Process Data ◽  
Embedded Devices ◽  
Communication Interface ◽  
Industrial Data ◽  
Manufacturing Execution Systems ◽  
Control Devices ◽  
Increasing Demand ◽  
Underlying Processes ◽  
Server Architecture

Contemporary computer systems used in the industry are characterized by both an increase in the scale of supported industrial processes measured by the number of control devices and the increasing demand for information describing the underlying processes measured by the number of tags used in Supervisory Control and Data Acquisition (SCADA) systems and Manufacturing Execution Systems (MES). Classical industrial data servers based on the PC architecture are unreliable, expensive to operate and difficult to manage. The alternative is a new standard OPC UA communication interface that simplifies the communication protocol and increases the flexibility of the process data description which allow for the direct implementation of OPC UA servers in embedded devices. This paper presents an innovative approaches in the field of industrial data servers which are used for communication between control systems and SCADA or MES systems. The prototype industrial data server architecture has been implemented, run and tested on the platform of embedded system based on FPGA matrix with built-in FPGA Microblaze processor. The presented experimental results allow to evaluate the applicability of the proposed solution, the limits of the presented architecture and may be used for the improvement of the embedded industrial data servers' structure in subsequent implementations.

scholarly journals A streaming multi-class support vector machine classification architecture for embedded systems

2019 ◽  
Vol 16 (3) ◽  
pp. 1286
Author(s):  
Jeevan Sirkunan ◽  
Jia Wei Tang ◽  
Nasir Shaikh-Husin ◽  
Muhammad Nadzir Marsono
Keyword(s):  
Embedded System ◽  
Test Data ◽  
Data Transfer ◽  
Pedestrian Detection ◽  
External Memory ◽  
Support Vector ◽  
Data Input ◽  
Maximum Throughput ◽  
Process Data ◽  
Svm Classification

<p>Pedestrian detection, face detection, speech recognition and object detection are some of the applications that have benefited from hardware-accelerated SVM. SVM classification computational complexity makes it challenging for designing hardware architecture with real-time performance and low power consumption. On an embedded streaming architecture, test data are stored on external memory and transferred in streams to the FPGA device. The hardware<br />implementation for SVM classification needs to be fast enough to keep up with the data transfer speed. Prior implementation throttles data input to avoid overwhelming the computational unit. This results in a bottleneck in overall streaming architecture as maximum throughput could not be obtained. In this work, we propose a streaming architecture multi-class SVM classification for embedded system that is fully pipelined and able to process data continuously with out any need to throttle data stream input. The proposed design is targeted for embedded platform where test data is transferred in streams from an external memory. The architecture was implemented on Altera Cyclone IV platform. Performance analysis on our proposed architecture is done with regards to the number of features and support vectors. For validation, the results obtained is compared with LibSVM. The proposed architecture is able to produce output rate identical to test data input rate.</p>

An Integrated Architectural Clock Implemented Memory Design for Embedded System

2015 ◽  
Vol 4 (2) ◽  
pp. 129
Author(s):  
Ravi Khatwal ◽  
Manoj Kumar Jain
Keyword(s):  
Embedded System ◽  
Low Power ◽  
Propagation Delay ◽  
Internal Clock ◽  
Access Time ◽  
Architecture Design ◽  
Embedded Devices ◽  
Memory Design ◽  
Simulation Performance ◽  
Cache Simulation

Recently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance for specific application. We have implemented clock based memory architecture design and analyzed internal clock efficiency for SRAM. Architectural clock implemented memory design that reduces access time and propagation delay time for embedded devices. Internal semiconductor material improvement increases simulation performance and these design implemented for application specific design architecture.

MANIPULATING THE POLARIZATION OF TERAHERTZ WAVES WITH METAMATERIAL DEVICES

2014 ◽  
Vol 02 (02) ◽  
pp. 1440008 ◽  
Author(s):  
LONGQING CONG ◽  
JIANQIANG GU ◽  
ZHEN TIAN ◽  
RANJAN SINGH ◽  
JIAGUANG HAN ◽  
...  
Keyword(s):  
Polarization State ◽  
Terahertz Waves ◽  
Optical Components ◽  
Polarization Control ◽  
Design Flexibility ◽  
Potential Applications ◽  
Excellent Control ◽  
Terahertz Frequencies ◽  
Control Devices ◽  
Increasing Demand

As the potential applications of terahertz science and technology become extremely important, there is an increasing demand for improved terahertz optical components. One of such devices on demand is the class of polarization control devices. Recently, metasurfaces have emerged as designer structures with excellent control, design flexibility, and multifaceted functionalities. Metamaterials offer fascinating prospects for manipulating the polarization state of terahertz waves. Here, we discuss different metamaterial device designs that exhibit properties of perfect linear polarization rotation and linear to either linear or circular polarization conversion at narrowband as well as broadband terahertz frequencies.

scholarly journals A Hardware Approach of a Low-Power IoT Communication Interface by NXP FlexIO Module

2019 ◽  
Vol 25 (6) ◽  
pp. 35-39
Author(s):  
Libor Chrastecky ◽  
Jaromir Konecny ◽  
Martin Stankus ◽  
Michal Prauzek
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Total Power ◽  
Processing Unit ◽  
Embedded Devices ◽  
Communication Interface ◽  
Result Section ◽  
Central Processing ◽  
Total Power Consumption ◽  
Software And Hardware

This article describes implementation possibilities of specialized microcontroller peripherals, as hardware solution for Internet of Things (IoT) low-power communication, interfaces. In this contribution, authors use the NXP FlexIO periphery. Meanwhile, RFC1662 is used as a reference communication standard. Implementation of RFC1662 is performed by software and hardware approaches. The total power consumption is measured during experiments. In the result section, authors evaluate a time-consumption trade-off between the software approach running in Central Processing Unit (CPU) and hardware implementation using NXP FlexIO periphery. The results confirm that the hardware-based approach is effective in terms of power consumption. This method is applicable in IoT embedded devices.

scholarly journals Self-Learning Pipeline for Low-Energy Resource-Constrained Devices

Energies ◽  
2021 ◽  
Vol 14 (20) ◽  
pp. 6636
Author(s):  
Fouad Sakr ◽  
Riccardo Berta ◽  
Joseph Doyle ◽  
Alessandro De De Gloria ◽  
Francesco Bellotti
Keyword(s):  
Embedded System ◽  
Nearest Neighbor ◽  
Energy Resource ◽  
K Nearest Neighbor ◽  
Resource Constrained ◽  
Confidence Measure ◽  
Embedded Devices ◽  
Remote Training ◽  
Iot Devices ◽  
Self Learning

The trend of bringing machine learning (ML) to the Internet of Things (IoT) field devices is becoming ever more relevant, also reducing the overall energy need of the applications. ML models are usually trained in the cloud and then deployed on edge devices. Most IoT devices generate large amounts of unlabeled data, which are expensive and challenging to annotate. This paper introduces the self-learning autonomous edge learning and inferencing pipeline (AEP), deployable in a resource-constrained embedded system, which can be used for unsupervised local training and classification. AEP uses two complementary approaches: pseudo-label generation with a confidence measure using k-means clustering and periodic training of one of the supported classifiers, namely decision tree (DT) and k-nearest neighbor (k-NN), exploiting the pseudo-labels. We tested the proposed system on two IoT datasets. The AEP, running on the STM NUCLEO-H743ZI2 microcontroller, achieves comparable accuracy levels as same-type models trained on actual labels. The paper makes an in-depth performance analysis of the system, particularly addressing the limited memory footprint of embedded devices and the need to support remote training robustness.

scholarly journals Multivariate Statistics Between Two-Observation Spaces

2022 ◽  
pp. 31-44
Author(s):  
Jing Wang ◽  
Jinglin Zhou ◽  
Xiaolu Chen
Keyword(s):  
Multivariate Statistics ◽  
Quality Data ◽  
Smart Manufacturing ◽  
Process Data ◽  
Industrial Data ◽  
Soft Measurement ◽  
Measurement Control ◽  
Manufacturing Problems

AbstractAs mentioned in the previous chapter, industrial data are usually divided into two categories, process data and quality data, belonging to different measurement spaces. The vast majority of smart manufacturing problems, such as soft measurement, control, monitoring, optimization, etc., inevitably require modeling the data relationships between the two kinds of measurement variables. This chapter’s subject is to discover the correlation between the sets in different observation spaces.

scholarly journals Software driven approach for Embedded Devices

2020 ◽  
pp. 01-08
Author(s):  
Hrvoje Dodig ◽  
Joško Šoda ◽  
Ivana Golub
Keyword(s):  
Embedded System ◽  
Working Hours ◽  
Software Components ◽  
New Paradigm ◽  
Embedded Devices ◽  
Electronic Circuitry ◽  
Communication Device ◽  
Embedded Design ◽  
Design Paradigm ◽  
The Embedded System

This paper presents the possible new design paradigm that emerged during the author’s design of an embedded communication device for Croatian Navy. Prior to codesign techniques that emerged in 1990's the traditional embedded design methodology involved problem specification, separate hardware and software specification, integration, and the system test as the final step in the embedded device design. Such an approach can potentially lead to numerous iterations and can increase the cost of the development cycle because there are no guarantees that separately developed software will work well with separately designed hardware. Codesign techniques, on the other hand, delay the decision to which components of hardware or software will be used for embedded system until late stages of embedded design process. At the time of the invention of the codesign techniques this seemed as perfectly balanced approach between design of hardware and software spending about equal time in the design of both hardware and software components. However, since the 1990’s the design of embedded devices has changed; nowadays the most working hours are spent in the design of software while the design of hardware requires less working hours due to extensive choice of IC’s and supporting electronic circuits, and due to advancement of EDA software tools. In favor of the software-driven approach presented in this paper, it should be noted that nowadays, there is a large number of freely-available software components and libraries which, if properly utilized, greatly expedite the development of the software part of the embedded system design. Therefore, perhaps it is a suitable time for a new paradigm shift where the design of the hardware is completely dictated by the design of software, and the design of the hardware is simply the matter of selecting proper IC’s and other electronic circuitry that supports the software. In this paper, we present an example of the embedded design using this software-driven design strategy. By the end of this paper, it is shown that software-driven design not only allows the rapid prototyping of embedded devices, but it reduces the possibility of design errors, as well. Keywords: Embedded design; Hardware-software codesign; Software driven design; ARM technology

Will Tomorrow’s Failure Analysis Lab Operate More Like Today’s Fab?

2014 ◽  
Author(s):  
Todd Templeton ◽  
Valerie Brogden
Keyword(s):  
Failure Analysis ◽  
Process Data ◽  
Increasing Demand ◽  
Operator Interaction

Abstract Efficiencies in operation are achieved largely in advanced failure analysis (FA) labs because routine steps or processes have been automated and the need for operator interaction minimized. Very few operators are required to run a fully automated, "lights out" type Fab. This paper discusses the various automation components which are available to labs as they look to streamline the FA process to support the Fab's ever increasing demand for more process data. These include iFast Automation software and automated recipes to create the thick lamella. The development of automation software and integrated accessories for FA equipment is now bringing more Fab-like activities and processes into the FA lab. As more and more automation moves into the FA lab, one should not be surprised in a few years to see very few operators sitting in front of tools with blinking green lights scattered throughout the lab.

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