A Mixed Signal DC Offset Cancellation for VGA of Zero-IF Receiver

2016 ◽  
Vol 26 (03) ◽  
pp. 1750047
Author(s):  
Yiqiang Zhao ◽  
Jingshuai Wang ◽  
Yun Sheng
Keyword(s):  
Calibration Method ◽  
Compensation Voltage ◽  
Digital Logic ◽  
Cmos Process ◽  
Mixed Signal ◽  
Offset Cancellation ◽  
Dc Offset ◽  
Measurement Results ◽  
Calibration Time

This paper proposes a mixed signal DC offset cancellation (DCOC) which does not cause the near-DC rejection for zero-IF receiver. To achieve low output offset efficiently, the DCOC consisting of a comparator, a digital logic controller and compensation voltage generators is used. It utilizes current sources arrays that are controlled by thermometer code to generate the compensation voltage. The proposed DCOC is implemented in GF 0.18 [Formula: see text]m CMOS process. The measurement results show that the proposed calibration method can reduce the offset residue to less than 80 mV and the total calibration time is less than 13 [Formula: see text]s. It only drains 60 [Formula: see text]A from a 3.3 V supply.

Research on Calibration Method of Three-Phase Smart Meter

2014 ◽  
Vol 556-562 ◽  
pp. 2043-2048
Author(s):  
Yong Jie Wang ◽  
Hui Zhang ◽  
Jie Ran Wang
Keyword(s):  
Theoretical Analysis ◽  
Measurement Accuracy ◽  
Reactive Power ◽  
Calibration Method ◽  
Active Power ◽  
Smart Meter ◽  
Practical Application ◽  
Dc Offset ◽  
Three Phase ◽  
Measurement Results

Specific to the parameters in the process of three-phase smart meter calibration, such as DC offset, AC offset, AC gain, etc. impact on measurement results, a design of a three-phase smart meter based on CS5463 chips is introduced in this paper. Through theoretical analysis, optimized calibration, and experimental verification, parameters such as voltage, current, active power, reactive power, apparent power, power factor can be measured by the meter. After calibrated, the voltage and current measurement accuracy of the three-phase smart meter can reach above 0.2%. It can meet the needs of the practical application.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

scholarly journals Cobot User Frame Calibration: Evaluation and Comparison between Positioning Repeatability Performances Achieved by Traditional and Vision-Based Methods

Robotics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 45
Author(s):  
Roberto Pagani ◽  
Cristina Nuzzi ◽  
Marco Ghidelli ◽  
Alberto Borboni ◽  
Matteo Lancini ◽  
...  
Keyword(s):  
Quantitative Analysis ◽  
Production Line ◽  
Calibration Method ◽  
Fiducial Marker ◽  
Positioning System ◽  
Local Calibration ◽  
Calibration Methods ◽  
Robot Positioning ◽  
Good Repeatability ◽  
Calibration Time

Since cobots are designed to be flexible, they are frequently repositioned to change the production line according to the needs; hence, their working area (user frame) needs to be often calibrated. Therefore, it is important to adopt a fast and intuitive user frame calibration method that allows even non-expert users to perform the procedure effectively, reducing the possible mistakes that may arise in such contexts. The aim of this work was to quantitatively assess the performance of different user frame calibration procedures in terms of accuracy, complexity, and calibration time, to allow a reliable choice of which calibration method to adopt and the number of calibration points to use, given the requirements of the specific application. This has been done by first analyzing the performances of a Rethink Robotics Sawyer robot built-in user frame calibration method (Robot Positioning System, RPS) based on the analysis of a fiducial marker distortion obtained from the image acquired by the wrist camera. This resulted in a quantitative analysis of the limitations of this approach that only computes local calibration planes, highlighting the reduction of performances observed. Hence, the analysis focused on the comparison between two traditional calibration methods involving rigid markers to determine the best number of calibration points to adopt to achieve good repeatability performances. The analysis shows that, among the three methods, the RPS one resulted in very poor repeatability performances (1.42 mm), while the three and five points calibration methods achieve lower values (0.33 mm and 0.12 mm, respectively) which are closer to the reference repeatability (0.08 mm). Moreover, comparing the overall calibration times achieved by the three methods, it is shown that, incrementing the number of calibration points to more than five, it is not suggested since it could lead to a plateau in the performances, while increasing the overall calibration time.

A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver

2021 ◽  
Author(s):  
Yunhee Lee ◽  
Woonghee Lee ◽  
Minkyo Shim ◽  
Deog-Kyoon Jeong
Keyword(s):  
Offset Cancellation ◽  
Dc Offset ◽  
Step Algorithm

scholarly journals A 5-Gb/s 66 dB CMOS Variable-Gain Amplifier With Reconfigurable DC-Offset Cancellation for Multi-Standard Applications

IEEE Access ◽  
2018 ◽  
Vol 6 ◽  
pp. 54139-54146 ◽  
Author(s):  
Zhiqing Liu ◽  
Yunqiu Wu ◽  
Chenxi Zhao ◽  
Johannes Benedikt ◽  
Kai Kang
Keyword(s):  
Variable Gain Amplifier ◽  
Offset Cancellation ◽  
Dc Offset ◽  
Variable Gain

Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

2012 ◽  
Author(s):  
Arjun Kar-Roy ◽  
Paul Hurwitz ◽  
Richard Mann ◽  
Yasir Qamar ◽  
Samir Chaudhry ◽  
...  
Keyword(s):  
Cmos Process ◽  
Mixed Signal ◽  
Technology Node

Study of Split Capacitor DAC Mismatch and Calibration in SAR-ADC

2016 ◽  
Vol 26 (01) ◽  
pp. 1750003
Author(s):  
Yun Zhang ◽  
Yiqiang Zhao ◽  
Peng Dai
Keyword(s):  
Calibration Method ◽  
Sar Adc ◽  
Calibration Error ◽  
Cmos Process ◽  
Analog To Digital ◽  
Significant Performance ◽  
Performance Deterioration ◽  
Conventional Structure ◽  
Split Capacitor ◽  
Simulation Results

Mismatch and parasitic effects of bridge capacitors in successive-approximation-register analog-to-digital converter’s (SAR-ADC) split capacitor digital-to-analog conversion (DAC) cause a significant performance deterioration. This paper presents a nonlinearity analysis based on an analytical model, and a modified calibration method utilizing a pre-bias bridge capacitor is accordingly proposed. The proposed method, which uses three-segment split capacitor DAC structure, can effectively eliminate over-calibration error caused by conventional structure. To verify the technique, a 14-bit SAR-ADC has been designed in 0.35-[Formula: see text]m 2P4M CMOS process with the PIP capacitor, and the simulation results show the method can further improve ADC performance.

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