Even with SiC power MOSFETs released into the commercial market, the threshold voltage instability caused by near interface states is still an attracting issue, which is a major obstacle to further improving the device performance. In this paper, the effects of temperature storage on the threshold voltage stability of n-channel 4H-SiC VDMOSFET are studied. It is found that the capture of hole traps is dominant during the long-term temperature storage at 425 K, causing a considerable negative shift of threshold voltage. In view of the influence of temperature storage, the positive and negative drift trends of threshold voltage slow down during the gate-bias stress measurement. And the ∆VTH, the difference between the threshold voltages recorded after positive and negative gate-bias stress in the same duration, also grows slowly with the increasing stress duration. Finally, some suggestions for improving the threshold reliability of n-channel SiC VDMOSFETs are presented.
