A Merged Single-Electron Transistor and Metal-Oxide-Semiconductor Transistor Logic for Interface and Multiple-Valued Functions

2002 ◽  
Vol 41 (Part 1, No. 4B) ◽  
pp. 2566-2568 ◽  
Author(s):  
Hiroshi Inokawa ◽  
Akira Fujiwara ◽  
Yasuo Takahashi
2011 ◽  
Vol 110-116 ◽  
pp. 5085-5089
Author(s):  
Khadijeh Feizi ◽  
Ali Shahhoseini

Adder is one of the important arithmetic units in computers. In this paper, we investigate the implementation of quaternary half adder based on multiple-valued (MV) logic gates using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. We use hybrid SETMOS universal literal gate which has been proposed by Mahapatra and Ionesco. We apply two 4-radix inputs to the proposed quaternary half adder and obtain sum and carry outputs. The logic operation of the proposed quaternary half adder is verified by using HSPICE simulator. Moreover we compare the performance of our proposed quaternary half adder with the performance of a quaternary half adder based on MOS technology.


2006 ◽  
Vol 89 (7) ◽  
pp. 073106 ◽  
Author(s):  
G. M. Jones ◽  
B. H. Hu ◽  
C. H. Yang ◽  
M. J. Yang ◽  
Russell Hajdaj ◽  
...  

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