Design of Quaternary Half Adder Using Hybrid SETMOS Cell

2011 ◽  
Vol 110-116 ◽  
pp. 5085-5089
Author(s):  
Khadijeh Feizi ◽  
Ali Shahhoseini
Keyword(s):  
Metal Oxide ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Single Electron ◽  
Oxide Semiconductor ◽  
Single Electron Transistor ◽  
Mos Transistor ◽  
Logic Operation ◽  
Half Adder ◽  
Arithmetic Units

Adder is one of the important arithmetic units in computers. In this paper, we investigate the implementation of quaternary half adder based on multiple-valued (MV) logic gates using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. We use hybrid SETMOS universal literal gate which has been proposed by Mahapatra and Ionesco. We apply two 4-radix inputs to the proposed quaternary half adder and obtain sum and carry outputs. The logic operation of the proposed quaternary half adder is verified by using HSPICE simulator. Moreover we compare the performance of our proposed quaternary half adder with the performance of a quaternary half adder based on MOS technology.

Enhancement-mode metal-oxide-semiconductor single-electron transistor on pure silicon

2006 ◽  
Vol 89 (7) ◽  
pp. 073106 ◽  
Author(s):  
G. M. Jones ◽  
B. H. Hu ◽  
C. H. Yang ◽  
M. J. Yang ◽  
Russell Hajdaj ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Single Electron ◽  
Oxide Semiconductor ◽  
Single Electron Transistor ◽  
Pure Silicon ◽  
Enhancement Mode

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

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