A Substrate Bias Effect on Recovery of the Threshold Voltage Shift of Amorphous Silicon Thin-Film Transistors

2007 ◽  
Vol 46 (7A) ◽  
pp. 4042-4045 ◽  
Author(s):  
Chang-Wook Han ◽  
Min-Koo Han ◽  
Nack-Bong Choi ◽  
Chang-Dong Kim ◽  
Ki-Yong Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Substrate Bias ◽  
Silicon Thin Film ◽  
Bias Effect ◽  
Threshold Voltage Shift ◽  
Voltage Shift

Threshold Voltage Shift of Amorphous Silicon Thin-Film Transistors During Pulse Operation

1991 ◽  
Vol 30 (Part 1, No. 12B) ◽  
pp. 3719-3723 ◽  
Author(s):  
Ryoji Oritsuki ◽  
Toshikazu Horii ◽  
Akira Sasano ◽  
Ken Tsutsui ◽  
Toshiko Koizumi ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Pulse Operation ◽  
Threshold Voltage Shift ◽  
Voltage Shift

Proximity Recovery Layers to Speed up the Recovery of Stressed Amorphous Silicon Thin-Film Transistors

1990 ◽  
Vol 192 ◽  
Author(s):  
M. Hack ◽  
W. B. Jackson ◽  
R. Lujan
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
High Voltage ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Hydrogenated Amorphous Silicon ◽  
Silicon Thin Film ◽  
Threshold Voltage Shift ◽  
Speed Up ◽  
Hydrogenated Amorphous

ABSTRACTWe have developed a means to speed up the recovery of both the threshold voltage shift of hydrogenated amorphous silicon (a-Si:H) transistors and the Vx shift of high voltage a-Si devices. This is accomplished by placing a lightly doped compensated layer adjacent to the active layer in these transistors. This proximity recovery layer does not alter the initial characteristics of a-Si:H transistors and is completely process compatible with standard fabrication procedures.

Abnormal Threshold Voltage Shifts in P-Channel Low-Temperature Polycrystalline Silicon Thin Film Transistors Under Negative Bias Temperature Stress

2015 ◽  
Vol 15 (10) ◽  
pp. 7555-7558 ◽  
Author(s):  
Sang Sub Kim ◽  
Pyung Ho Choi ◽  
Do Hyun Baek ◽  
Jae Hyeong Lee ◽  
Byoung Deog Choi
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Charge Trapping ◽  
Trap States ◽  
Silicon Thin Film ◽  
Threshold Voltage Shift ◽  
Voltage Shift

In this research, we have investigated the instability of P-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) with double-layer SiO2/SiNX dielectrics. A negative gate bias temperature instability (NBTI) stress was applied and a turn-around behavior phenomenon was observed in the Threshold Voltage Shift (Vth). A positive threshold voltage shift occurs in the first stage, resulting from the negative charge trapping at the SiNX/SiO2 dielectric interface being dominant over the positive charge trapping at dielectric/Poly-Si interface. Following a stress time of 7000 s, the Vth switches to the negative voltage direction, which is “turn-around” behavior. In the second stage, the Vth moves from −1.63 V to −2 V, overwhelming the NBTI effect that results in the trapping of positive charges at the dielectric/Poly-Si interface states and generating grain-boundary trap states and oxide traps.

scholarly journals Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 327
Author(s):  
Je-Hyuk Kim ◽  
Jun Tae Jang ◽  
Jong-Ho Bae ◽  
Sung-Jin Choi ◽  
Dong Myong Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Oxygen Content ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Electron Trapping ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Drain Side ◽  
Bottom Gate

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Investigation on the Electrical Stability of 5,11-Bis(triethylsilylethynyl)anthradithiophene Thin-Film Transistors

2021 ◽  
Vol 21 (3) ◽  
pp. 1754-1760
Author(s):  
Joel Ndikumana ◽  
Jyothi Chintalapalli ◽  
Jin-Hyuk Kwon ◽  
Jin-Hyuk Bae ◽  
Jaehoon Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Ambient Air ◽  
Gate Insulator ◽  
Hydroxyl Groups ◽  
Electrical Stability ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Domain Boundaries

We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.

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