Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function

2008 ◽  
Vol 47 (6) ◽  
pp. 4385-4391 ◽  
Author(s):  
Kyoung-Rok Han ◽  
Byung-Kil Choi ◽  
Hyuck-In Kwon ◽  
Jong-Ho Lee
Keyword(s):  
Work Function ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor ◽  
Gate Work Function

The device level modulation of carrier transport in a 2D WSe2 field effect transistor via a plasma treatment

Nanoscale ◽  
2019 ◽  
Vol 11 (37) ◽  
pp. 17368-17375 ◽  
Author(s):  
Inyong Moon ◽  
Sungwon Lee ◽  
Myeongjin Lee ◽  
Changsik Kim ◽  
Daehee Seol ◽  
...  
Keyword(s):  
Plasma Treatment ◽  
Work Function ◽  
Field Effect ◽  
Carrier Transport ◽  
Field Effect Transistor ◽  
Plasma Channel ◽  
Thermal Limit ◽  
Channel Resistance ◽  
Effect Transistor

WSe2 FET oxidized by plasma. Channel resistance decreases exponentially with increasing WSe2 work function, approaching thermal limit.

Fabrication and Characterization of Graphene Field Effect Transistor: Study of Interfacial Effects for Device Reliability

2015 ◽  
Vol 36 ◽  
pp. 8-15
Author(s):  
Neetu Prasad ◽  
Anita Kumari ◽  
P.K. Bhatnagar ◽  
P.C. Mathur
Keyword(s):  
Work Function ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Interfacial Effects ◽  
Small Series ◽  
Increase With Increase ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor ◽  
Mos Device

In the present work, we report fabrication and electrical characterization of a back gated graphene field effect transistor (GFET). We have focused our study on the interfacial effect (graphene/SiO2) on the performance of the device. Hysteresis was observed in the drain conductance when measured with respect to dual gate sweep voltage, which increases with increasing sweeping voltage range. The conductance was observed to increase with increase in temperature but there was no reduction in the hysteresis. This proved that temperature annealing could improve the channel conductivity but not the interfacial effects. Further, a metal oxide semiconductor (MOS) device was fabricated with SLG inserted in between the metal and oxide layer and its capacitance-voltage (C-V) characteristics were studied. A small series capacitance (2.1 nF) was observed to be existing in series with the oxide capacitance (4.5 nF) which was attributed to the trap states at the interface of graphene and SiO2­ layer. Also, the flat band voltage was not affected by the incorporation of graphene layer in the MOS device indicating no change in the work function of the metal gate (Cr/Au). This is an advantageous situation where graphene does not alter its work function also being impermeable, restricts the diffusion of metal particles through the SiO2.

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