scholarly journals Declarative Power Sequencing

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-21
Author(s):  
Jasmin Schult ◽  
Daniel Schwyn ◽  
Michael Giardino ◽  
David Cock ◽  
Reto Achermann ◽  
...  
Keyword(s):  
High Performance ◽  
Power Delivery ◽  
System Component ◽  
Critical Element ◽  
Security Threat ◽  
Correct Operation ◽  
Power Delivery Networks ◽  
Modern Computer ◽  
Power Models ◽  
Efficient Power

Modern computer server systems are increasingly managed at a low level by baseboard management controllers (BMCs). BMCs are processors with access to the most critical parts of the platform, below the level of OS or hypervisor, including control over power delivery to every system component. Buggy or poorly designed BMC software not only poses a security threat to a machine, it can permanently render the hardware inoperative. Despite this, there is little published work on how to rigorously engineer the power management functionality of BMCs so as to prevent this happening. This article takes a first step toward putting BMC software on a sound footing by specifying the hardware environment and the constraints necessary for safe and correct operation. This is best accomplished through automation: correct-by-construction power control sequences can be efficiently generated from a simple, trustworthy model of the platform’s power tree that incorporates the sequencing requirements and safe voltage ranges of all components. We present both a modeling language for complex power-delivery networks and a tool to automatically generate safe, efficient power sequences for complex modern platforms. This not only increases the trustworthiness of a hitherto opaque yet critical element of platform firmware: regulator and chip power models are significantly simpler to produce than hand-written power sequences. This, combined with model reuse for common components, reduces both time and cost associated with platform bring-up for new hardware. We evaluate our tool using a new high-performance 2-socket server platform with >100W per socket TDP, tight voltage limits and 25 distinct power regulators needing configuration, showing both fast (<10s) tool runtime, and correct power sequencing of a live system.

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

Neural Network Inversion-Based Model for Predicting an Optimal Hardware Configuration

2021 ◽  
Vol 13 (2) ◽  
pp. 95-117
Author(s):  
Mirvat Mahmoud Al-Qutt ◽  
Heba Khaled ◽  
Rania El Gohary
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
High Performance ◽  
Function Optimization ◽  
Machine Learning Techniques ◽  
Problem Size ◽  
Neural Network Inversion ◽  
Computationally Intensive ◽  
Prediction Systems ◽  
Efficient Power

Deciding the number of processors that can efficiently speed-up solving a computationally intensive problem while perceiving efficient power consumption constitutes a major challenge to researcher in the HPC high performance computing realm. This paper exploits machine learning techniques to propose and implement a recommender system that recommends the optimal HPC architecture given the problem size. An approach for multi-objective function optimization based on neural network (neural network inversion) is employed. The neural network inversion approach is used for forward problem optimization. The objective functions in concern are maximizing the speedup and minimizing the power consumption. The recommendations of the proposed prediction systems achieved more than 89% accuracy for both validation and testing set. The experiments were conducted on 2500 CUDA core on Tesla K20 Kepler GPU Accelerator and Intel(R) Xeon(R) CPU E5-2695 v2.

Locality-Awareness and Replication for an Adaptive CHORD to MANet

2017 ◽  
Vol 8 (3) ◽  
pp. 1-24
Author(s):  
Sarra Cherbal ◽  
Abdellah Boukerram ◽  
Abdelhak Boubetra
Keyword(s):  
Energy Consumption ◽  
Mobile Ad Hoc Networks ◽  
High Performance ◽  
Ad Hoc ◽  
Critical Element ◽  
P2p Systems ◽  
Content Sharing ◽  
Wired Networks ◽  
Mobile Ad Hoc ◽  
Hoc Networks

Structured peer-to-peer (P2P) systems have shown over time a high performance to P2P users. They are typically applied on Internet and wired networks. On the other hand, the evolution of mobile devices and the popularity of infrastructure-less wireless networks as mobile ad-hoc networks (MANET), make of them an interesting underlay for P2P overlays. However, their energy consumption stills a critical element with limited-energy batteries, and the most principal cause of energy consumption is the immense overhead. The aim of this work is to apply the Chord protocol on MANET underlay, in order to benefit from the efficient content-sharing process and the infrastructure-less mobility. At the same time, this work aims to conserve a good level of energy consumption and network lifetime. Therefore, it proposes a novel mechanism of locality awareness and replication of data that attempts to improve the lookup efficiency and reduce the traffic overhead.

scholarly journals An efficient classification algorithm for NGS data based on text similarity

2018 ◽  
Vol 100 ◽  
Author(s):  
Xiangyu Liao ◽  
Xingyu Liao ◽  
Wufei Zhu ◽  
Lu Fang ◽  
Xing Chen
Keyword(s):  
High Performance ◽  
High Throughput Sequencing ◽  
Hash Table ◽  
Classification Algorithm ◽  
Sequencing Data ◽  
Text Similarity ◽  
Short Text ◽  
Time Consumption ◽  
Modern Computer ◽  
Ngs Data

AbstractWith the advancement of high-throughput sequencing technologies, the amount of available sequencing data is growing at a pace that has now begun to greatly challenge the data processing and storage capacities of modern computer systems. Removing redundancy from such data by clustering could be crucial for reducing memory, disk space and running time consumption. In addition, it also has good performance on reducing dataset noise in some analysis applications. In this study, we propose a high-performance short sequence classification algorithm (HSC) for next generation sequencing (NGS) data based on efficient hash function and text similarity. First, HSC converts all reads into k-mers, then it forms a unique k-mer set by merging the duplicated and reverse complementary elements. Second, all unique k-mers are stored in a hash table, where the k-mer string is stored in the key field, and the ID of the reads containing the k-mer are stored in the value field. Third, each hash unit is transformed into a short text consisting of reads. Fourth, texts that satisfy the similarity threshold are combined into a long text, the merge operation is executed iteratively until there is no text that satisfies the merge condition. Finally, the long text is transformed into a cluster consisting of reads. We tested HSC using five real datasets. The experimental results showed that HSC cluster 100 million short reads within 2 hours, and it has excellent performance in reducing memory consumption. Compared to existing methods, HSC is much faster than other tools, it can easily handle tens of millions of sequences. In addition, when HSC is used as a preprocessing tool to produce assembly data, the memory and time consumption of the assembler is greatly reduced. It can help the assembler to achieve better assemblies in terms of N50, NA50 and genome fraction.

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