Leakage Current Analysis of Lateral p+/n Ge Based Diode Activated at Low Temperature for Three-Dimensional Integrated Circuit (3D-ICs)

Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.

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Dielectric GlueWafer Bonding For 3D ICs

MRS Proceedings ◽

10.1557/proc-766-e5.8 ◽

2003 ◽

Vol 766 ◽

Cited By ~ 11

Author(s):

Y. Kwon ◽

A. Jinda ◽

J.J. McMahon ◽

J.Q. Lu ◽

R.J. Gutmann ◽

...

Keyword(s):

Integrated Circuit ◽

Bonding Strength ◽

Three Dimensional ◽

Wafer Level ◽

Four Point Bending ◽

Mechanical And Electrical Properties ◽

3D Ics ◽

Bond Interface ◽

Three Dimensional Integrated Circuit ◽

Wafer Thinning

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

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A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

Micro and Nanosystems ◽

10.2174/1876402912666200123154001 ◽

2020 ◽

Vol 12 ◽

Author(s):

Kang-Jia Wang ◽

Hong-Chang Sun ◽

Kui-Zhi Wang

Keyword(s):

Integrated Circuit ◽

Heat Dissipation ◽

Three Dimensional ◽

Micro Channel ◽

3D Ic ◽

Through Silicon Vias ◽

3D Ics ◽

Three Dimensional Integrated Circuit ◽

Silicon Vias ◽

Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

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Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications

Nanomaterials ◽

10.3390/nano10122488 ◽

2020 ◽

Vol 10 (12) ◽

pp. 2488

Author(s):

Siqi Tang ◽

Jiang Yan ◽

Jing Zhang ◽

Shuhua Wei ◽

Qingzhu Zhang ◽

...

Keyword(s):

Low Temperature ◽

Integrated Circuits ◽

Integrated Circuit ◽

Low Cost ◽

Silicon Nanowire ◽

Three Dimensional ◽

Sensor Arrays ◽

Processing Temperature ◽

C 30 ◽

Three Dimensional Integrated Circuit

In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

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