Dielectric GlueWafer Bonding For 3D ICs

2003 ◽  
Vol 766 ◽  
Author(s):  
Y. Kwon ◽  
A. Jinda ◽  
J.J. McMahon ◽  
J.Q. Lu ◽  
R.J. Gutmann ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Bonding Strength ◽  
Three Dimensional ◽  
Wafer Level ◽  
Four Point Bending ◽  
Mechanical And Electrical Properties ◽  
3D Ics ◽  
Bond Interface ◽  
Three Dimensional Integrated Circuit ◽  
Wafer Thinning

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

High Density Direct Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications

2006 ◽  
Vol 970 ◽  
Author(s):  
Paul Enquist
Keyword(s):  
Wafer Bonding ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
High Density ◽  
Temperature Cycling ◽  
Direct Wafer Bonding ◽  
Part Yield ◽  
Bond Interface ◽  
Bonding Technology ◽  
Three Dimensional Integrated Circuit

ABSTRACTA novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability × 10 greater than the JEDEC requirement, connection yield ∼ 99.999, > 50% part yield on parts with ∼ 450,000 connections, and < 0.1 Ohm connection resistance at 1pA without requiring a voltage surge to induce current.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Micro Channel ◽  
3D Ic ◽  
Through Silicon Vias ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit ◽  
Silicon Vias ◽  
Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs

2005 ◽  
Author(s):  
R. J. Gutmann ◽  
J. J. McMahon ◽  
J.-Q. Lu
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Three Dimensional ◽  
Wafer Level ◽  
3D Integration ◽  
3D Ics ◽  
Technology Platforms ◽  
Technology Focus ◽  
Feature Scale ◽  
Ic Technology

Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm–1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.

Leakage Current Analysis of Lateral p+/n Ge Based Diode Activated at Low Temperature for Three-Dimensional Integrated Circuit (3D-ICs)

2019 ◽  
Vol 33 (12) ◽  
pp. 35-39
Author(s):  
Woo Shik Jung ◽  
Jin Hong Park ◽  
Duygu Kuzum ◽  
Wanki Kim ◽  
Simon Wong ◽  
...  
Keyword(s):  
Low Temperature ◽  
Leakage Current ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Current Analysis ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit

Enhancement of through Silicon via Sidewall Quality by Nanosecond Laser Pulses with Chemical Etching Process

2012 ◽  
Vol 579 ◽  
pp. 3-9 ◽  
Author(s):  
Chao Wei Tang ◽  
Shih Chieh Tseng ◽  
Hong Tsu Young ◽  
Kuan Ming Li ◽  
Mike Yang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Chemical Etching ◽  
Three Dimensional ◽  
Laser Pulses ◽  
Nanosecond Laser ◽  
Wafer Level ◽  
Sidewall Roughness ◽  
Through Silicon Via ◽  
Three Dimensional Integrated Circuit ◽  
Micrometer Scale

Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system in package, and wafer level packaging applications. In this study, a wet chemical etching (WCE) process has been employed to enhance the sidewall quality of TSVs fabricated using nanosecond (ns) laser pulses. Experimental results show that the TSV sidewall roughness can be markedly reduced, from micrometer scale to nanometer scale. We concluded that the proposed method would enable semiconductor manufactures to use ns laser drilling for industrial TSV fabrication as the desired TSV sidewall quality can be achieved by incorporating the WCE process, which is suitable for mass production.

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