Effect of Buffer LiF Layer on Nonvolatile Memory Characteristics for Polymer Memory-cell with Au Nanocrystals Embedded in Polystyrene

2012 ◽  
Vol 52 (8) ◽  
pp. 1627-1631 ◽  
Author(s):  
Jer-Chyi Wang ◽  
Chih-Ting Lin ◽  
Chi-Hsien Huang ◽  
Chao-Sung Lai ◽  
Chin-Hsiang Liao

2008 ◽  
Vol 1071 ◽  
Author(s):  
Chia-Han Yang ◽  
Yue Kuo ◽  
Chen-Han Lin ◽  
Rui Wan ◽  
Way Kuo

AbstractSemiconducting or metallic nanocrystals embedded high-k films have been investigated. They showed promising nonvolatile memory characteristics, such as low leakage currents, large charge storage capacities, and long retention times. Reliability of four different kinds of nanocrystals, i.e., nc- Ru, -ITO, -Si and -ZnO, embedded Zr-doped HfO2 high-k dielectrics have been studied. All of them have higher relaxation currents than the non-embedded high-k film has. The decay rate of the relaxation current is in the order of nc-ZnO > nc-ITO > nc-Si > nc-Ru. When the relaxation currents of the nanocrystals embedded samples were fitted to the Curie-von Schweidler law, the n values were between 0.54 and 0.77, which are much lower than that of the non embedded high-k sample. The nanocrystals retain charges in two different states, i.e., deeply and loosely trapped. The ratio of these two types of charges was estimated. The charge storage capacity and holding strength are strongly influenced by the type of material of the embedded nanocrystals. The nc-ZnO embedded film holds trapped charges longer than other embedded films do. The ramp-relax result indicates that the breakdown of the embedded film came from the breakdown of the bulk high-k film. The type of nanocrystal material influences the breakdown strength.


2019 ◽  
Vol 19 (1) ◽  
pp. 41-47
Author(s):  
Chia-Han Yang ◽  
Yue Kuo ◽  
Chen-Han Lin ◽  
Way Kuo

Author(s):  
Sharon Cui ◽  
Dongseog Eun ◽  
Bozidar Marinkovic ◽  
Cheng-Yi Peng ◽  
Xiao Pan ◽  
...  

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.


2013 ◽  
Vol 14 (5) ◽  
pp. 1231-1236 ◽  
Author(s):  
Min-Hoi Kim ◽  
Gyu Jeong Lee ◽  
Chang-Min Keum ◽  
Sin-Doo Lee

2012 ◽  
Vol 101 (3) ◽  
pp. 033501 ◽  
Author(s):  
L. Liu ◽  
J. P. Xu ◽  
F. Ji ◽  
J. X. Chen ◽  
P. T. Lai

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