Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Heechun Park ◽  
Bon Woong Ku ◽  
Kyungwook Chang ◽  
Da Eun Shim ◽  
Sung Kyu Lim
Keyword(s):  
State Of The Art ◽  
Physical Design ◽  
Design Flow ◽  
Design Tools ◽  
Mixed Design ◽  
Power Performance ◽  
3D Design ◽  
Qualitative And Quantitative ◽  
3D Ics ◽  
Power Delay Product

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

scholarly journals An enhancement of the current design concepts for the improved consideration of residual stresses in fatigue-loaded welds

2021 ◽  
Vol 65 (4) ◽  
pp. 643-651
Author(s):  
Th. Nitschke-Pagel ◽  
J. Hensel
Keyword(s):  
Residual Stresses ◽  
State Of The Art ◽  
High Strength Steels ◽  
High Strength ◽  
Design Tools ◽  
Design Concepts ◽  
Treatment Processes ◽  
Real Distribution ◽  
Current Design ◽  
Reliable Knowledge

AbstractThe consideration of residual stresses in fatigue-loaded welds is currently done only qualitatively without reliable knowledge about their real distribution, amount and prefix. Therefore, the tools which enable a more or less unsafe consideration in design concepts are mainly based on unsafe experiences and doubtful assumptions. Since the use of explicitly determined residual stresses outside the welding community is state of the art, the target of the presented paper is to show a practicable way for an enhanced consideration of residual stresses in the current design tools. This is not only limited on residual stresses induced by welding, but also on post-weld treatment processes like HFMI or shot peening. Results of extended experiments with longitudinal fillet welds and butt welds of low and high strength steels evidently show that an improved use of residual stresses in fatigue strength approximation enables a better evaluation of peening processes as well as of material adjusted welding procedures or post-weld stress relief treatments. The concept shows that it is generally possible to overcome the existing extremely conservative but although unsafe rules and regulations and may also enable the improved use of high strength steels.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

scholarly journals Learning a Generative Model for Fusing Infrared and Visible Images via Conditional Generative Adversarial Network with Dual Discriminators

2019 ◽  
Author(s):  
Han Xu ◽  
Pengwei Liang ◽  
Wei Yu ◽  
Junjun Jiang ◽  
Jiayi Ma
Keyword(s):  
Probability Distribution ◽  
State Of The Art ◽  
Infrared Image ◽  
Infrared Images ◽  
Generative Adversarial Network ◽  
Visible Image ◽  
Qualitative And Quantitative ◽  
Adversarial Network ◽  
Fused Image ◽  
Visible Images

In this paper, we propose a new end-to-end model, called dual-discriminator conditional generative adversarial network (DDcGAN), for fusing infrared and visible images of different resolutions. Unlike the pixel-level methods and existing deep learning-based methods, the fusion task is accomplished through the adversarial process between a generator and two discriminators, in addition to the specially designed content loss. The generator is trained to generate real-like fused images to fool discriminators. The two discriminators are trained to calculate the JS divergence between the probability distribution of downsampled fused images and infrared images, and the JS divergence between the probability distribution of gradients of fused images and gradients of visible images, respectively. Thus, the fused images can compensate for the features that are not constrained by the single content loss. Consequently, the prominence of thermal targets in the infrared image and the texture details in the visible image can be preserved or even enhanced in the fused image simultaneously. Moreover, by constraining and distinguishing between the downsampled fused image and the low-resolution infrared image, DDcGAN can be preferably applied to the fusion of different resolution images. Qualitative and quantitative experiments on publicly available datasets demonstrate the superiority of our method over the state-of-the-art.

Approximate Full Adders for Energy Efficient Image Processing Applications

2021 ◽  
pp. 2150235
Author(s):  
M. C. Parameshwara
Keyword(s):  
Energy Efficient ◽  
State Of The Art ◽  
Signal To Noise Ratio ◽  
Full Adder ◽  
Signal To Noise ◽  
Design Metrics ◽  
Standard Cell Library ◽  
Cell Library ◽  
Fair Comparison ◽  
Power Delay Product

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB. And the AFA2 has the total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB.

Physical Design Flow for 3D /CoWoS® Stacked IC s

2019 ◽  
pp. 81-114
Author(s):  
Yu‐Shiang Lin ◽  
Sandeep K. Goel ◽  
Jonathan Yuan ◽  
Tom Chen ◽  
Frank Lee
Keyword(s):  
Physical Design ◽  
Design Flow

A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding

2020 ◽  
Vol 39 (10) ◽  
pp. 2152-2165
Author(s):  
Huanyu Wang ◽  
Qihang Shi ◽  
Adib Nahiyan ◽  
Domenic Forte ◽  
Mark M. Tehranipoor
Keyword(s):  
Physical Design ◽  
Design Flow ◽  
Front Side ◽  
Probing Attacks
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