scholarly journals VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-23 ◽  
Author(s):  
Gottfried Fuchs ◽  
Andreas Steininger
Keyword(s):  
Fault Tolerant ◽  
Single Point ◽  
Asynchronous Design ◽  
Clock Generation ◽  
Future Technology ◽  
Novel Approach ◽  
Measurement Results ◽  
Crystal Oscillators ◽  
On Chip ◽  
Technology Nodes

We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply–properties that are considered highly desirable for future technology nodes.

A New Fault Tolerant Routing Algorithm for Networks on Chip

2019 ◽  
Vol 10 (3) ◽  
pp. 68-85
Author(s):  
Chakib Nehnouh ◽  
Mohamed Senouci
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Transient Faults ◽  
Networks On Chip ◽  
Congestion Detection ◽  
Novel Approach ◽  
On Chip ◽  
Detection Mechanisms ◽  
Correct Data

To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free and congestion-free zones.

scholarly journals A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour

2020 ◽  
Author(s):  
Masaru Fukushi ◽  
Yota Kurokawa
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Slight Modification ◽  
Routing Algorithms ◽  
Future Research ◽  
Communication Performance ◽  
Novel Approach ◽  
Average Latency ◽  
The Common ◽  
On Chip

Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable Network-on-Chip (NoC) systems with high communication performance. In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms in NoCs. The common idea of the fault-tolerant routing has been undoubtedly to detour faulty nodes, while our approach allows passing through faulty nodes with the slight modification of NoC architecture. As a design example, we present an XY-based routing algorithm with the passage function. To investigate the effect of the approach, we compare the communication performance (i.e. average latency) of the XY-based algorithm with well-known region-based algorithms under the condition of with and without virtual channels. Finally, we provide possible directions of future research on the fault-tolerant routing with the passage function.

scholarly journals Impact of Bundle Structure on Performance of on-Chip CNT Interconnects

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Nisha Kuruvilla ◽  
J. P. Raina
Keyword(s):  
Deep Submicron ◽  
Worst Case ◽  
Optimum Performance ◽  
Future Technology ◽  
Performance Predictions ◽  
Metallic Cnts ◽  
Swcnts And Mwcnts ◽  
On Chip ◽  
Technology Nodes ◽  
Bundle Structure

CNTs are proposed as a promising candidate against copper in deep submicron IC interconnects. Still this technology is in its infancy. Most available literatures on performance predictions of CNT interconnects, have focused only on interconnect geometries using segregated CNTs. Yet during the manufacturing phase, CNTs are obtained usually as a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). Especially in case of SWCNTs; it is usually available as a mixture of both Semi conducting CNTs and metallic CNTs. This paper attempts to answer whether segregation is inevitable before using them to construct interconnects. This paper attempt to compare the performance variations of bundled CNT interconnects, where bundles are made of segregated CNTs versus mixed CNTs, for future technology nodes using electrical model based analysis. Also a proportionate mixing of different CNTs has been introduced so as to yield a set of criteria to aid the industry in selection of an appropriate bundle structure for use in a specific application with optimum performance. It was found that even the worst case performance of geometries using a mixture of SWCNTs and MWCNTs was better than copper. These results also reveal that, for extracting optimum performance vide cost matrix, the focus should be more on diameter controlled synthesis than on segregation.

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