scholarly journals Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Fang Tang ◽  
Amine Bermak ◽  
Abbes Amira ◽  
Mohieddine Amor Benammar ◽  
Debiao He ◽  
...  
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Sar Adc ◽  
Quantization Noise ◽  
Noise Performance ◽  
Chip Area ◽  
Full Resolution

Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

scholarly journals [Paper] A 20Mfps Global Shutter CMOS Image Sensor with Improved Light Sensitivity and Power Consumption Performances

2016 ◽  
Vol 4 (2) ◽  
pp. 149-154 ◽  
Author(s):  
Rihito Kuroda ◽  
Yasuhisa Tochigi ◽  
Ken Miyauchi ◽  
Tohru Takeda ◽  
Hidetake Sugo ◽  
...  
Keyword(s):  
Power Consumption ◽  
Cmos Image Sensor ◽  
Light Sensitivity ◽  
Image Sensor

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

An 8-bit column-shared SAR ADC for CMOS image sensor applications

2015 ◽  
Author(s):  
Jin-Yi Lin ◽  
Kwuang-Han Chang ◽  
Chen-Che Kao ◽  
Shih-Chin Lo ◽  
Yan-Jiun Chen ◽  
...  
Keyword(s):  
Cmos Image Sensor ◽  
Image Sensor ◽  
Sar Adc ◽  
Sensor Applications

Color mixing improvement of CMOS image sensor with air-gap-guard ring in deep-submicrometer CMOS technology

2005 ◽  
Vol 26 (5) ◽  
pp. 301-303 ◽  
Author(s):  
T.H. Hsu ◽  
Y.K. Fang ◽  
D.N. Yaung ◽  
S.G. Wuu ◽  
H.C. Chien ◽  
...  
Keyword(s):  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Air Gap ◽  
Guard Ring ◽  
Deep Submicrometer ◽  
Color Mixing

scholarly journals A CMOS voltage-mode image sensing system

2021 ◽  
Author(s):  
Jun Long Zhang
Keyword(s):  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Electrical Signal ◽  
Image Sensors ◽  
Analog To Digital ◽  
Light Sensing ◽  
Image Sensing ◽  
Cmos Image Sensors ◽  
Pixel Sensors

A CMOS image sensor consists of a light sensing region that converts photonic energy to an electrical signal and a peripheral circuitry that performs signal conditioning and post-processing. This project investgates the principle and design of CMOS active image sensors. The basic concepts and principle of CMOS image sensors are investigated. The advantages of CMOS image sensors over charge-coupled device (CCD) image sensors are presented. Both passive pixel sensors (PPS) and acive pixel sensors (APS) are examined in detail. The noise of CMOS image sensors is investigated and correlated double sampling (CDS) techniques are examined. The design of APS arrays, CDS circuits and 8-bit analog to-digital converters in TSMC-0.18μm 1.8V CMOS technology is presented. The simulation results and layout of the designed CMOS image sensor are presented.

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