[Paper] A 20Mfps Global Shutter CMOS Image Sensor with Improved Light Sensitivity and Power Consumption Performances

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

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Low Power Consumption Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters for 33-Megapixel 120-fps CMOS Image Sensor

The Journal of The Institute of Image Information and Television Engineers ◽

10.3169/itej.67.j286 ◽

2013 ◽

Vol 67 (8) ◽

pp. J286-J295

Author(s):

Toshihisa Watabe ◽

Kazuya Kitamura ◽

Takehide Sawamoto ◽

Tomohiko Kosugi ◽

Tomoyuki Akahori ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

Cmos Image Sensor ◽

Image Sensor ◽

Analog To Digital Converters ◽

Low Power Consumption ◽

Two Stage ◽

Analog To Digital ◽

Cyclic Analog

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5.5 A 2.1e− Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063092 ◽

2020 ◽

Author(s):

Jae-Kyu Lee ◽

Seung Sik Kim ◽

In-Gyu Baek ◽

Heesung Shim ◽

Taehoon Kim ◽

...

Keyword(s):

High Capacity ◽

Cmos Image Sensor ◽

Light Sensitivity ◽

Image Sensor ◽

Temporal Noise ◽

Backside Illuminated

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Continuous-TimeΣΔADC with Implicit Variable Gain Amplifier for CMOS Image Sensor

The Scientific World JOURNAL ◽

10.1155/2014/208540 ◽

2014 ◽

Vol 2014 ◽

pp. 1-7 ◽

Cited By ~ 1

Author(s):

Fang Tang ◽

Amine Bermak ◽

Amira Abbes ◽

Mohieddine Amor Benammar

Keyword(s):

Power Consumption ◽

Cmos Image Sensor ◽

Image Sensor ◽

Variable Gain Amplifier ◽

Cmos Process ◽

Clock Frequency ◽

Pixel Resolution ◽

Loop Filter ◽

Sigma Delta ◽

Variable Gain

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

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A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

Sensors ◽

10.3390/s20020486 ◽

2020 ◽

Vol 20 (2) ◽

pp. 486

Author(s):

Ken Miyauchi ◽

Kazuya Mori ◽

Toshinori Otaka ◽

Toshiyuki Isozaki ◽

Naoto Yasuda ◽

...

Keyword(s):

Dynamic Range ◽

High Sensitivity ◽

Cmos Image Sensor ◽

Light Sensitivity ◽

Image Sensor ◽

Motion Artifacts ◽

Oxide Semiconductor ◽

Storage Capacitor ◽

Cmos Process ◽

Back Side

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

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Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

The Scientific World JOURNAL ◽

10.1155/2014/861278 ◽

2014 ◽

Vol 2014 ◽

pp. 1-6 ◽

Cited By ~ 6

Author(s):

Fang Tang ◽

Amine Bermak ◽

Abbes Amira ◽

Mohieddine Amor Benammar ◽

Debiao He ◽

...

Keyword(s):

Power Consumption ◽

Error Correction ◽

Cmos Image Sensor ◽

Cmos Technology ◽

Image Sensor ◽

Sar Adc ◽

Quantization Noise ◽

Noise Performance ◽

Chip Area ◽

Full Resolution

Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

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