scholarly journals A Novel Generalized Memristor Based on Three-Phase Diode Bridge Rectifier

Complexity ◽  
2019 ◽  
Vol 2019 ◽  
pp. 1-8
Author(s):  
Chaojun Wu ◽  
Ningning Yang ◽  
Cheng Xu ◽  
Rong Jia ◽  
Chongxin Liu
Keyword(s):  
Hysteresis Loops ◽  
Normal Operation ◽  
Rectifier Circuit ◽  
The Third ◽  
Three Phase ◽  
Bridge Rectifier ◽  
Pinched Hysteresis Loop ◽  
Intersection Points ◽  
Simulation Results ◽  
Pinched Hysteresis

Memristive characteristics in three-phase diode bridge rectifier circuit are proposed in this paper. The conduction of the diodes is discussed and the characteristics of the pinched hysteresis loop are analyzed by both numerical simulations and circuit simulations. The hysteresis loops of each phase not only are pinched at the origin but also have the other two intersection points in the first quadrant and the third quadrant when three-phase bridge rectifier circuit is running under normal operation. Other conditions are also discussed when a variety of faults conditions occur. The simulation results verify that the three-phase bridge rectifier circuit can be described as a generalized memristor element during several operation states.

scholarly journals CMOS Realization of All-Positive Pinched Hysteresis Loops

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
B. J. Maundy ◽  
A. S. Elwakil ◽  
C. Psychalinos
Keyword(s):  
Hysteresis Loop ◽  
Detailed Analysis ◽  
Hysteresis Loops ◽  
Nonlinear Circuits ◽  
Experimental Results ◽  
First Order ◽  
Pinched Hysteresis Loop ◽  
A Charge ◽  
Pinched Hysteresis ◽  
Nmos Transistors

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.

New Grounded and Floating Memristor-Less Meminductor Emulators Using VDTA and CDBA

2021 ◽  
pp. 2150283
Author(s):  
Nisha Yadav ◽  
Shireesh Kumar Rai ◽  
Rishikesh Pandey
Keyword(s):  
Adaptive Learning ◽  
Hysteresis Loops ◽  
Cmos Technology ◽  
Chaotic Oscillator ◽  
Simulation Tool ◽  
Analog Multiplier ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Pinched Hysteresis

In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2[Formula: see text]MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180[Formula: see text]nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.

A Novel Bipolar Photon-Controlled Generalized Memristor Based on Avalanche Photodiode

2020 ◽  
pp. 2150090
Author(s):  
Jianxiu Hao ◽  
Xiangliang Jin ◽  
Bo Peng
Keyword(s):  
Topological Structure ◽  
Hysteresis Loops ◽  
Avalanche Photodiode ◽  
Circuit Model ◽  
Traditional Model ◽  
Circuit Simulator ◽  
Dynamical Characteristics ◽  
Spice Model ◽  
Pinched Hysteresis Loop ◽  
Pinched Hysteresis

A novel bipolar photon-controlled generalized memristor model with an avalanche photodiode (APD) passive quenching circuit is presented in this paper. The SPICE model of the circuit is established and its fingerprints are analyzed by the pinched hysteresis loops with different bipolar periodic stimuli. The dynamical characteristics of the proposed circuit model are investigated both theoretically and simulatively. The results verified by Cadence Spectre circuit simulator demonstrate that the proposed circuit model is a simple bipolar photon-controlled generalized memristor. Compared with the previously published memristor models, the biggest innovation of this paper is to propose a bipolar generalized memristor model instead of the traditional model, which can easily form the pinched hysteresis loop. Another highlight is that the generalized memristor model in this paper is controlled by photons while conventional memristors are charge-controlled/flux-controlled. Furthermore, the circuit level models are more stable, more reliable and more resistant to interference than the device level models. The topological structure of the proposed circuit model in this paper is much more simpler.

Computing Areas of Pinched Hysteresis Loops of Mem-Systems in OrCAD PSPICE

2013 ◽  
Vol 278-280 ◽  
pp. 1081-1090 ◽  
Author(s):  
Dalibor Biolek ◽  
Zdenek Biolek ◽  
Viera Biolkova ◽  
Zdenek Kolka
Keyword(s):  
Hysteresis Loop ◽  
Memory Effect ◽  
Hysteresis Loops ◽  
Simulation Software ◽  
Excitation Signal ◽  
Pspice Simulation ◽  
Special Cases ◽  
Special Measuring ◽  
Pinched Hysteresis Loop ◽  
Pinched Hysteresis

The pinched hysteresis loop belongs to the fingerprints of the so-called mem-systems, their well-known special cases being memristors. The memory effect of the system is determined by the area of the curve lobes which gradually decrease with increasing repeating frequency of the excitation signal. The paper describes a method for automated computation of the above areas via the commonly utilized OrCAD PSpice simulation software with the help of special measuring functions of the PROBE postprocessor. The usefulness of the method is illustrated on an example of the analysis of a TiO2 memristor.

Fault Diagnosis Method for Rectifier Circuit Based on Self-Organizing Map

2013 ◽  
Vol 321-324 ◽  
pp. 1930-1933 ◽  
Author(s):  
Run Xia Shen ◽  
Yi Min Lu ◽  
Qian Qian Liang
Keyword(s):  
Feature Extraction ◽  
Fault Diagnosis ◽  
Self Organizing Map ◽  
Rectifier Circuit ◽  
Three Phase ◽  
Bridge Rectifier ◽  
Diagnosis Method ◽  
Fault Feature Extraction ◽  
Relevant Experiment ◽  
Self Organizing

Fault feature extraction and recognition play crucial role in fault diagnosis. In this paper, a fault diagnosis method for three-phase fully-controlled bridge rectifier circuit based on Self-Organizing Map network is proposed. The method utilized the three phase AC input current as fault detection data. Then, perform spectrum analysis with the FFT, the fault data is trained through a Self-Organizing Map network for diagnosis. Simulation and relevant experiment verifying the proposed algorithm can classify various types of power electronics device faults accurately and rapidly.

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