New Grounded and Floating Memristor-Less Meminductor Emulators Using VDTA and CDBA

2021 ◽  
pp. 2150283
Author(s):  
Nisha Yadav ◽  
Shireesh Kumar Rai ◽  
Rishikesh Pandey
Keyword(s):  
Adaptive Learning ◽  
Hysteresis Loops ◽  
Cmos Technology ◽  
Chaotic Oscillator ◽  
Simulation Tool ◽  
Analog Multiplier ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Pinched Hysteresis

In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2[Formula: see text]MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180[Formula: see text]nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.

scholarly journals Gm-Realization of Controlled-Gain Current Follower Transconductance Amplifier

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Worapong Tangsrirat
Keyword(s):  
Current Mode ◽  
Cmos Technology ◽  
Current Transfer ◽  
Biquad Filter ◽  
Transconductance Amplifier ◽  
Current Follower ◽  
Dc Bias ◽  
Simulation Results ◽  
Supply Voltages ◽  
A Current

This paper describes the conception of the current follower transconductance amplifier (CFTA) with electronically and linearly current tunable. The newly modified element is realized based on the use of transconductance cells (Gms) as core circuits. The advantage of this element is that the current transfer ratios (iz/ipandix/iz) can be tuned electronically and linearly by adjusting external DC bias currents. The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. As an application example, a current-mode KHN biquad filter is designed and simulated.

A New Floating Memristor Based on CBTA with Grounded Capacitors

2019 ◽  
Vol 28 (13) ◽  
pp. 1950217 ◽  
Author(s):  
Abdullah Yesil ◽  
Yunus Babacan ◽  
Fırat Kacar
Keyword(s):  
Integrated Circuit ◽  
Active Element ◽  
Supply Voltage ◽  
Bias Current ◽  
Analog Multiplier ◽  
Power Supply Voltage ◽  
Dc Power ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Memristor Emulator

This paper presents a new floating memristor emulator (FME) consisting of only a single current backward transconductance amplifier (CBTA) as the active element and two grounded capacitors. The proposed FME-based on CBTA enjoys some advantages that include minimum active and passive elements without using an analog multiplier circuit and grounded passive elements which are attractive for the integrated circuit. In addition, excluding the DC power supply voltage, it does not use bias voltage and/or bias current. The designed memristor circuit provides incremental and decremental characteristics without changing circuit topology or using a switching mechanism and it is implemented with a minimum of circuit elements. All simulation results for the memristor emulator were obtained as expected when compared with fabricated memristors.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Current Mirror ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Theory Analysis ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Simulation Results

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

scholarly journals A Novel Generalized Memristor Based on Three-Phase Diode Bridge Rectifier

Complexity ◽  
2019 ◽  
Vol 2019 ◽  
pp. 1-8
Author(s):  
Chaojun Wu ◽  
Ningning Yang ◽  
Cheng Xu ◽  
Rong Jia ◽  
Chongxin Liu
Keyword(s):  
Hysteresis Loops ◽  
Normal Operation ◽  
Rectifier Circuit ◽  
The Third ◽  
Three Phase ◽  
Bridge Rectifier ◽  
Pinched Hysteresis Loop ◽  
Intersection Points ◽  
Simulation Results ◽  
Pinched Hysteresis

Memristive characteristics in three-phase diode bridge rectifier circuit are proposed in this paper. The conduction of the diodes is discussed and the characteristics of the pinched hysteresis loop are analyzed by both numerical simulations and circuit simulations. The hysteresis loops of each phase not only are pinched at the origin but also have the other two intersection points in the first quadrant and the third quadrant when three-phase bridge rectifier circuit is running under normal operation. Other conditions are also discussed when a variety of faults conditions occur. The simulation results verify that the three-phase bridge rectifier circuit can be described as a generalized memristor element during several operation states.

Fully Electronically Tunable and Easily Cascadable Square/Triangular Wave Generator with Duty Cycle Adjustment

2019 ◽  
Vol 28 (06) ◽  
pp. 1950105 ◽  
Author(s):  
Bhartendu Chaturvedi ◽  
Atul Kumar
Keyword(s):  
Duty Cycle ◽  
Current Mode ◽  
Cmos Technology ◽  
Triangular Wave ◽  
Square Wave ◽  
Generator Circuit ◽  
Transconductance Amplifier ◽  
Wave Generator ◽  
Simulation Results ◽  
Triangular Wave Generator

A novel multiple-output dual-X current conveyor transconductance amplifier with buffer-based square/triangular wave generator is introduced in the paper. The proposed generator provides square wave in current mode and triangular wave in voltage mode. Outputs as square and triangular waves are available from terminals with appropriate impedance levels thereby making the proposed generator circuit easily cascadable in both current and voltage modes. The oscillation frequency and amplitude of output square wave are electronically and independently controllable. One more interesting feature of the proposed generator circuit is the adjustable duty cycle. The proposed circuit of square/triangular wave generator is verified through the HSPICE simulation results carried using 0.18[Formula: see text][Formula: see text]m CMOS technology. The simulation results show linear variation of duty cycle against external DC current over a range of 6.5–96%. The variation of square wave’s amplitude via bias current is found to be linear from 10[Formula: see text][Formula: see text]A to 80[Formula: see text][Formula: see text]A. Moreover, the proposed generator can operate very well up to 23.8[Formula: see text]MHz with nonlinearity less than 5%. The proposed generator circuit is also experimentally verified.

Memristor Emulator Circuit Using Multiple-Output OTA and Its Experimental Results

2019 ◽  
Vol 28 (10) ◽  
pp. 1950166 ◽  
Author(s):  
Rajeev Kumar Ranjan ◽  
Pankaj Kumar Sharma ◽  
Sagar ◽  
Niranjan Raj ◽  
Bharti Kumari ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Experimental Results ◽  
Active Device ◽  
Pass Filter ◽  
Transconductance Amplifier ◽  
Pinched Hysteresis Loop ◽  
A Charge ◽  
Memristor Emulator ◽  
High Pass ◽  
Pinched Hysteresis

A charge-controlled memristor emulator circuit based on one kind of active device [operational transconductance amplifier (OTA)] using CMOS technology is introduced in this paper. The proposed circuit can be configured in both incremental and decremental types by using a simple switch. The memristor behavior can be electronically tuned by adjusting the transconductance of the OTAs. By changing the value of the capacitor, the pinched hysteresis loop observed in the current versus voltage plane can be held at higher frequencies. The proposed emulator circuit functions well up to 500 kHz. The experiment has been performed using commercially available OTA ICs (CA3080). The experimental demonstration has been carried out for 10, 20 and 120[Formula: see text]kHz. A simple high-pass filter is explained in both configurations to demonstrate the functionality of the proposed memristor emulator. The proposed circuit has been simulated in PSPICE using 0.5-[Formula: see text]m CMOS parameter. The simulated and experimental results validate the theoretical proposition.

Novel Meminductor Emulators Using Operational Amplifiers and their Applications in Chaotic Oscillators

2021 ◽  
pp. 2150219
Author(s):  
Aneet Singh ◽  
Shireesh Kumar Rai
Keyword(s):  
Hysteresis Loop ◽  
Operational Amplifier ◽  
Experimental Results ◽  
Operational Amplifiers ◽  
Chaotic Oscillator ◽  
Chaotic Oscillators ◽  
Wide Range ◽  
Pinched Hysteresis Loop ◽  
Simulation Results ◽  
Pinched Hysteresis

This paper presents six different meminductor emulator circuits based on operational amplifiers. Five circuits of meminductor emulators have been proposed using two operational amplifiers, one memristor, three resistors and one capacitor, whereas the sixth circuit uses two operational amplifiers, two memristors, one resistor and two capacitors. All circuits of the proposed meminductor emulators are very simple over most of the realizations of meminductor emulators in the literature. The behaviors of meminductor emulators are satisfactory over a wide range of frequencies. The proposed configurations of meminductor emulators have been simulated by the LTspice tool. The SPICE models of both operational amplifier (AD711) and memristor have been used for simulation. The workability of the proposed meminductor emulators has also been verified using the basic and well-known structure of operational amplifier. In addition, the pinched hysteresis loop obtained by the simulation results of meminductor emulator has been achieved by the experimental results as well. Chaotic oscillator has been designed using the proposed meminductor emulator to prove the worthiness of the design.

Simulation Tool for Assignment Models: SIMASI

2014 ◽  
Vol 13 (8) ◽  
pp. 4723-4728
Author(s):  
Pratiksha Saxena ◽  
Smt. Anjali
Keyword(s):  
Optimization Procedure ◽  
Simulation Tool ◽  
Optimization Strategy ◽  
Performance Measurements ◽  
Integrated Simulation ◽  
Assignment Model ◽  
Classical Models ◽  
Simulation Results ◽  
User Friendly ◽  
Assignment Models

In this paper, an integrated simulation optimization model for the assignment problems is developed. An effective algorithm is developed to evaluate and analyze the back-end stored simulation results. This paper proposes simulation tool SIMASI (Simulation of assignment models) to simulate assignment models. SIMASI is a tool which simulates and computes the results of different assignment models. This tool is programmed in DOT.NET and is based on analytical approach to guide optimization strategy. Objective of this paper is to provide a user friendly simulation tool which gives optimized assignment model results. Simulation is carried out by providing the required values of matrix for resource and destination requirements and result is stored in the database for further comparison and study. Result is obtained in terms of the performance measurements of classical models of assignment system. This simulation tool is interfaced with an optimization procedure based on classical models of assignment system. The simulation results are obtained and analyzed rigorously with the help of numerical examples. 

Computer simulation to evaluate the economics of landfill gas recovery

1998 ◽  
Vol 38 (2) ◽  
pp. 201-208
Author(s):  
M. W. Milke
Keyword(s):  
Computer Simulation ◽  
Computer Program ◽  
Landfill Gas ◽  
Base Case ◽  
Simulation Tool ◽  
Hypothetical Case ◽  
Gas Recovery ◽  
Fixed Set ◽  
Key Variables ◽  
Simulation Results

A need exists for tools to improve evaluations of the economics of landfill gas recovery. A computer simulation tool is presented. It uses a spreadsheet computer program to calculate the economics for a fixed set of inputs, and a simulation program to consider variations in the inputs. The method calculates the methane generated each year, and estimates the costs and incomes associated with the recovery and sale of the gas. Base case results are presented for a city of 500,000. An uncertainty analysis for a hypothetical case is presented. The simulation results can help an analyst see the key variables affecting the economics of a project.

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

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