scholarly journals High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Cong Wei ◽  
Jianhan Wu ◽  
Rongshan Wei ◽  
Minghua He
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Efficiency ◽  
Harmonic Distortion ◽  
Utilization Rate ◽  
High Fidelity ◽  
Digital To Analog Converter ◽  
Interpolation Filter ◽  
Class D ◽  
Pulse Width Modulator

This study presents a high-fidelity and high-efficiency digital class-D audio power amplifier (CDA), which consists of digital and analog modules. To realize a compatible digital input, a fully digital audio digital-to-analog converter (DAC) is implemented on MATLAB and Xilinx System Generator, which consists of a 16x interpolation filter, a fourth-order four-bit quantized delta-sigma (ΔΣ) modulator, and a uniform-sampling pulse width modulator. The CDA utilizes the closed-loop negative feedback and loop-filtering technologies to minimize distortion. The audio DAC, which is based on a field-programmable gate array, consumes 0.128 W and uses 7100 LUTs, which achieves 11.2% of the resource utilization rate. The analog module is fabricated in a 0.18 µm BCD technology. The postlayout simulation results show that the CDA delivers an output power of 1 W with 93.3% efficiency to a 4 Ω speaker and achieves 0.0138% of the total harmonic distortion (THD) with a transient noise for a 1 kHz input sinusoidal test tone and 3.6 V supply. The output power reaches up to 2.73 W for 1% THD (with transient noise). The proposed amplifier occupies an active area of 1 mm2.

Study of Harmonic Suppression Method Based on the Class D Amplifier

2013 ◽  
Vol 273 ◽  
pp. 384-388
Author(s):  
Yu Guo ◽  
Wei Li
Keyword(s):  
Power Amplifier ◽  
Integrated Circuit ◽  
High Efficiency ◽  
Harmonic Distortion ◽  
Harmonic Suppression ◽  
Output Terminal ◽  
Class D Amplifier ◽  
Class D ◽  
Small Distortion ◽  
Harmonic Components

Class D power amplifier has the advantages of simple structure, small volume, high efficiency, large output power, and small distortion, therefore is applied widely in the audio power amplifier integrated circuit. But because of existing higher harmonic components, the total harmonic distortion (THD) is high. In this paper, for the characteristics of class D amplifier, a feed-forward control circuit is added to the amplifier output terminal, and a composite filter is used to inhibit output harmonics further. The simulation results show that, the method can reduce the system THD effectively and improve the performance of the amplifier.

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
High Efficiency ◽  
Common Source ◽  
Power Performance ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Saturated Output Power

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

scholarly journals A Power Amplifier with Large High-Efficiency Range for 5G Communication

Sensors ◽  
2020 ◽  
Vol 20 (19) ◽  
pp. 5581
Author(s):  
Zhiwei Zhang ◽  
Zhiqun Cheng ◽  
Guohua Liu
Keyword(s):  
Output Power ◽  
Design Process ◽  
Power Amplifier ◽  
High Efficiency ◽  
New Method ◽  
Saturated Output Power ◽  
Doherty Power Amplifier ◽  
5G Communication

This paper presents a new method to design a Doherty power amplifier (DPA) with a large, high-efficiency range for 5G communication. This is through analyzing the drain-to-source capacitance (CDS) of DPAs, and adopting appropriate impedance of the peak device. A closed design process is proposed, to design the extended efficiency range DPA based on derived theories. For validation, a DPA with large efficiency range was designed and fabricated by using two equal devices. The measured results showed that the saturated output power was between 43.4 dBm and 43.7 dBm in the target band. Around 70% saturated drain efficiency is obtained with a gain of greater than 11 dB. Moreover, the obtained drain efficiency is larger than 50% at the 10 dB power back-off, when operating at 3.5 GHz. These superior performances illustrate that the implemented DPA can be applied well in 5G communication.

A High-Efficiency Cascade Multilevel Class-D Amplifier

2012 ◽  
Vol 482-484 ◽  
pp. 559-564
Author(s):  
Guo Hua Xu ◽  
Ying Zhang ◽  
Ming Dong ◽  
Lu Wei Xu
Keyword(s):  
Sliding Mode Control ◽  
Power Amplifier ◽  
High Efficiency ◽  
Sliding Mode ◽  
Mathematic Model ◽  
Total System ◽  
Mode Control ◽  
Class D Amplifier ◽  
Class D ◽  
The Individual

A switch-mode power amplifier based on a cascaded multicell multilevel circuit topology is introduced in the paper. Due to the Carrier-Based phase-shifted modulation of the individual switching cells, the output voltage ripple of the total system is considerably small. Compared with traditional class- AB amplifiers that are very poor at efficiency, the proposed amplifier has the efficiency of 90% at the smaller distortion level. A multilevel class-D amplifier’s mathematic model is analyzed. The paper lays emphasis on the design of the sliding mode control and deducts the parameters, and then develops a 2kW cascade multilevel class-D power amplifier adopting sliding mode control. The research results show that this kind of amplifier increases the system bandwidth, which provides the system with fast following performance and stability, high efficiency, and low THD value of output signals.

scholarly journals Design of a Class-D Audio Amplifier With Analog Volume Control for Mobile Applications

2016 ◽  
Vol 62 (2) ◽  
pp. 187-196
Author(s):  
Karim El khadiri ◽  
Hassan Qjidaa
Keyword(s):  
Power Efficiency ◽  
High Efficiency ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Volume Control ◽  
Ramp Generator ◽  
Audio Amplifier ◽  
Class D ◽  
Level Shifter ◽  
Programmable Gain

Abstract A class-D audio amplifier with analog volume control (AVC) for portable applications is proposed in this paper. The proposed class-D consist of two sections. First section is an analog volume control which consists of an integrator, an analog MUX and a programmable gain amplifier (PGA). The AVC is implemented with three analog inputs (Audio, Voice, FM). Second section is a driver which consists of a ramp generator, a comparator, a level shifter and a gate driver. The driver is designed to obtain a low distortion and a high efficiency. Designed with 0.18 um 1P6M CMOS technology, the class-D audio amplifier with AVC achieves a total root-mean-square (RMS) output power of 0.5W, a total harmonic distortion plus noise (THD+N) at the 8-Ω load less than 0.06% and a power efficiency of 90% with a total area of 1.74 mm2.

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