scholarly journals Logic Design and Power Optimization of Floating-Point Multipliers

2022 ◽  
Vol 2022 ◽  
pp. 1-10
Author(s):  
Na Bai ◽  
Hang Li ◽  
Jiming Lv ◽  
Shuai Yang ◽  
Yaohua Xu
Keyword(s):  
Power Consumption ◽  
Power Optimization ◽  
Current Situation ◽  
Floating Point ◽  
Cell Process ◽  
Logic Design ◽  
Flowing Water ◽  
Partial Product ◽  
Standard Cell ◽  
Single Precision

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symbolic expansion idea, and the partial product caused by single-precision floating-point multiplication and the accumulation of partial products are optimized, and the flowing water is used to improve the throughput. Based on this, a series of verification and synthesis simulations are performed using the SMIC-7 nm standard cell process. It is verified that the new single-precision floating-point multiplier can achieve a smaller power share compared to the conventional single-precision floating-point multiplier.

scholarly journals Approximate Reciprocal Square Root with Single - and Half-Precision Floats

2018 ◽  
Author(s):  
Matheus M. Susin ◽  
Lucas Wanner
Keyword(s):  
Power Consumption ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Approximation Techniques ◽  
Point Number ◽  
Floating Point Number ◽  
Floating Point Numbers

In this work, we compared the precision, speed, and power consumption of the reciprocal square root of a single-precision floating point number, using different approximation techniques. We also devised an equivalent approximation for half-precision floating point numbers, and evaluated its performance across the whole range of positive non-zero 16-bit floating point values.

scholarly journals A Low-Cost High Radix Floating-Point Square-Root Circuit

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1988
Author(s):  
Yuheng Yang ◽  
Qing Yuan ◽  
Jian Liu
Keyword(s):  
Power Consumption ◽  
Low Cost ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Dynamic Power ◽  
Low Area ◽  
High Radix

In this paper, we propose an efficient architecture of floating-point square-root circuit with low area cost, which is in accordance with the IEEE-754 standard. We extend the principle of the standard SRT algorithm so that the latency and area cost of the proposed circuit are linear with the radix. In addition, no extra computation cycles are required. With 65 nm technology, the area cost of the single-precision floating-point square-root circuit based on proposed architecture is only 6450.84 μm2, and the dynamic power consumption is only 0.764 mW at 300 MHz. The implementation results show that the proposed square-root circuit can reduce the area cost by 60%~90% compared with other designs in the literature.

Dynamic modeling and power optimization of a 4RPSP+PS parallel flight simulator machine

Robotica ◽  
2021 ◽  
pp. 1-26
Author(s):  
Soheil Zarkandi
Keyword(s):  
Power Consumption ◽  
Dynamic Modeling ◽  
Parallel Manipulator ◽  
Degrees Of Freedom ◽  
Pareto Front ◽  
Essential Role ◽  
Power Optimization ◽  
Optimal Designs ◽  
Flight Simulator ◽  
Lagrange Method

Abstract Reducing consumed power of a robotic machine has an essential role in enhancing its energy efficiency and must be considered during its design process. This paper deals with dynamic modeling and power optimization of a four-degrees-of-freedom flight simulator machine. Simulator cabin of the machine has yaw, pitch, roll and heave motions produced by a 4RPSP+PS parallel manipulator (PM). Using the Euler–Lagrange method, a closed-form dynamic equation is derived for the 4RPSP+PS PM, and its power consumption is computed on the entire workspace. Then, a newly introduced optimization algorithm called multiobjective golden eagle optimizer is utilized to establish a Pareto front of optimal designs of the manipulator having a relatively larger workspace and lower power consumption. The results are verified through numerical examples.

scholarly journals Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2990-2993
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Single Precision ◽  
Vedic Mathematics ◽  
Quadruple Precision

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

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