scholarly journals Coding Schemes for Implementation of Fault Tolerant Parrallel Filter

2018 ◽  
Vol 7 (4) ◽  
pp. 353
Author(s):  
Nutenki Siddhartha ◽  
G. Renuka
Keyword(s):  
Field Programmable Gate Array ◽  
Digital Filters ◽  
Fault Tolerant ◽  
Structure And Properties ◽  
Coding Schemes ◽  
Coding Systems ◽  
Field Programmable ◽  
Parallel Channels ◽  
The Cost

<em>Digital filters are utilized as a one of flag handling and correspondence frameworks. At times, the unwavering quality of those frameworks is basic, and blame tolerant channel executions are needed. Throughout the years, numerous systems that endeavor the channels' structure and properties to accomplish adaptation to internal failure have been proposed. As innovation scales, it empowers more unpredictable frameworks that join many channels. In those perplexing frameworks, it is regular that a portion of the channels work in parallel. A plan in view of big rectification coding has been as of late proposed to protect parallel channels. In that plan, each channel is deal with as a bit, and excess channels that go about as equality check bits are acquainted with distinguish and rectify blunders. In this short, applying coding systems to secure parallel channels is tended to in a more broad manner. This decreases the assurance overhead and makes the quantity of excess channels autonomous of the quantity of parallel channels. The proposed technique is first described and then illustrated with two case studies. Finally, both the effectiveness in protecting against errors and the cost are evaluated for a field-programmable gate array implementation.</em>

An Accelerator for Decoding Market Data Based on FPGA

2019 ◽  
Vol 28 (03) ◽  
pp. 1950050
Author(s):  
Yuhao Dou ◽  
Yisu Zhou ◽  
Bo Xin
Keyword(s):  
Information Exchange ◽  
Field Programmable Gate Array ◽  
Financial Information ◽  
Low Latency ◽  
Market Data ◽  
Field Programmable ◽  
Leading Position ◽  
Average Latency ◽  
The Cost ◽  
Securities Trading

In securities trading, low latency helps investors take the leading position in the market. Conventionally, market data is decoded with software running on general computers. However, the serial structure of software and complex operating system scheduling cause high latency. This paper designs an accelerator for decoding market data based on field-programmable gate array (FPGA). We propose a pipeline in the accelerator, where every part works independently and parallelly. Furthermore, we present a mechanism for encoding templates, which avoids reconstructing the accelerator and decreases the cost when the template is renewed. We evaluate this accelerator with real Financial Information eXchange (FIX) messages and FIX Adapting for Streaming (FAST) templates, attaining an average latency of 447[Formula: see text]ns.

Optimization of Advanced Signal Processing Architectures for Detection of Signals Immersed in Noise

2016 ◽  
pp. 171-212
Author(s):  
Marcos A. Funes ◽  
Matías N. Hadad ◽  
Patricio G. Donato ◽  
Daniel O. Carrica
Keyword(s):  
Signal Processing ◽  
Field Programmable Gate Array ◽  
Processing Scheme ◽  
Coding Schemes ◽  
Radar Systems ◽  
Complementary Sequences ◽  
Field Programmable ◽  
Processing Architectures ◽  
Detection Of Signals ◽  
Application Fields

The use of Field Programmable Gate Array (FPGA) devices in the signal processing field has been on a constant rise since the beginning of the last decade. In particular, in the field of signal processing applications, the implementation of methods and techniques for the detection of coded signals immersed in noise should be highlighted. In this chapter, focus is placed on a special type of coding known as Complementary Sequences, and on some of the coding schemes derived from them. These sequences have been employed in many different application fields, ranging from safety sensors and radar systems to communications and material characterization. Specifically, this chapter deals with issues related to algorithms improvement and to their implementation in FPGA platforms, with particular emphasis on hardware resources efficiency and on the reliability of the whole processing scheme.

scholarly journals OPTIMIZATION OF 2D LATTICE CELLULAR AUTOMATA FOR PSEUDORANDOM NUMBER GENERATION

2005 ◽  
Vol 16 (03) ◽  
pp. 479-500 ◽  
Author(s):  
MARIE THERESE ROBLES QUIETA ◽  
SHENG-UEI GUAN
Keyword(s):  
Genetic Algorithm ◽  
Cellular Automata ◽  
Neighborhood Characteristics ◽  
Structure And Properties ◽  
Pseudorandom Number Generation ◽  
The Cost ◽  
Number Of Cells ◽  
Better Than ◽  
2D Array

This paper proposes a generalized approach to 2D CA PRNGs — the 2D lattice CA PRNG — by introducing vertical connections to arrays of 1D CA. The structure of a 2D lattice CA PRNG lies in between that of 1D CA and 2D CA grid PRNGs. With the generalized approach, 2D lattice CA PRNG offers more 2D CA PRNG variations. It is found that they can do better than the conventional 2D CA grid PRNGs. In this paper, the structure and properties of 2D lattice CA are explored by varying the number and location of vertical connections, and by searching for different 2D array settings that can give good randomness based on Diehard test. To get the most out of 2D lattice CA PRNGs, genetic algorithm is employed in searching for good neighborhood characteristics. By adopting an evolutionary approach, the randomness quality of 2D lattice CA PRNGs is optimized. In this paper, a new metric, #rn is introduced as a way of finding a 2D lattice CA PRNG with the least number of cells required to pass Diehard test. Following the introduction of the new metric #rn, a cropping technique is presented to further boost the CA PRNG performance. The cost and efficiency of 2D lattice CA PRNG is compared with past works on CA PRNGs.

scholarly journals IMPROVING FPGA COMPONENTS OF CRITICAL SYSTEMS BASED ON NATURAL VERSION REDUNDANCY

2021 ◽  
Vol 4 (2) ◽  
pp. 168-177
Author(s):  
Oleksandr V. Drozd ◽  
Andrzej Rucinski ◽  
Kostiantyn V. Zashcholkin ◽  
Myroslav O. Drozd ◽  
Yulian Yu. Sulima
Keyword(s):  
Normal Mode ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Fault Tolerant ◽  
Normal Operation ◽  
Functional Safety ◽  
Critical Systems ◽  
Program Code ◽  
Field Programmable ◽  
Emergency Mode

The article is devoted to the problem of improving FPGA (Field Programmable Gate Array) components developed for safety related systems. FPGA components are improved in the checkability of their circuits and the trustworthiness of the results calculated on them to support fault-tolerant solutions, which are basic in ensuring the functional safety of critical systems. Fault-tolerant solu tions need protection from sources of multiple failures, which include hidden faults. They can be accumulated in significant quanti ties during a long normal operation and disrupt the functionality of fault-tolerant circuits with the onset of the most responsible emer gency mode. Protection against hidden faults is ensured by the checkability of the circuits, which is aimed at the manifestation of faults and therefore must be supported in conjunction with the trustworthiness of the results, taking into account the decrease in trustworthiness in the event of the manifestation of faults. The problem of increasing the checkability of the FPGA component in normal operation and the trustworthiness of the results calculated in the emergency mode is solved by using the natural version re dundancy inherent in the LUT-oriented architecture (Look-Up Table). This redundancy is manifested in the existence of many ver sions of the program code that preserve the functionality of the FPGA component with the same hardware implementation. The checkability of the FPGA component and the trustworthiness of the calculated results are considered taking into account the typical failures of the LUT-oriented architecture. These malfunctions are investigated from the standpoint of the consistency of their mani festation and masking, respectively, in normal and emergency modes on versions of the program code. Malfunctions are identified with bit distortion in the memory of the LUT units. Bits that are only observed in emergency mode are potentially dangerous because they can hide faults in normal mode. Moving potentially dangerous bits to checkable positions, observed in normal mode, is per formed by choosing the appropriate versions of the program code and organizing the operation of the FPGA component on several versions. Experiments carried out with the FPGA component using the example of an iterative array multiplier of binary codes have shown the effectiveness of using the natural version redundancy of the LUT-oriented architecture to solve the problem of hidden faults.

A DISTRIBUTED APPROXIMATION ALGORITHM FOR FAULT-TOLERANT METRIC FACILITY LOCATION

2011 ◽  
Vol 22 (05) ◽  
pp. 1019-1034
Author(s):  
SHIHONG XU ◽  
HONG SHEN
Keyword(s):  
Approximation Algorithm ◽  
Facility Location ◽  
Fault Tolerant ◽  
Optimal Solution ◽  
Facility Location Problem ◽  
The Cost ◽  
Distributed Approximation ◽  
Special Case ◽  
Connection Cost

In this paper, we propose an approximation algorithm for the Fault-Tolerant Metric Facility Location problem which can be implemented in a distributed and asynchronous manner within O(n) rounds of communication, where n is the number of vertices in the network. Given a constant size set [Formula: see text] which represents distinct levels of fault-tolerant requirements of all cities, as well as the two-part (facility and connection) cost of the optimal solution, i.e. F* + C*, the cost of our solution is no more than [Formula: see text] for the general case, and less than F* + 2C* for the special case where all cities have a uniform connectivity requirement. Extensive numerical experiments showed that the quality of our solutions is comparable (within 4% error) to the optimal solution in practice.

Using Transportation Accident Databases in Human Factors Research

1992 ◽  
Vol 36 (13) ◽  
pp. 965-969
Author(s):  
David L. Mayer ◽  
Vernon S. Ellingstad
Keyword(s):  
Human Factors ◽  
Coding Schemes ◽  
Coding Systems ◽  
Common Causes ◽  
Accident Data ◽  
The Common ◽  
File Structures ◽  
Human Factors Research ◽  
Transportation Accident

Accident databases commonly contain factual information about the time and date of each accident, vehicle characteristics, number of persons killed and injured, and other kinds of factual data. These attributes of the environment and equipment are usually directly represented in databases. In contrast, detailed analysis of accident causes, including human factors information, are frequently not represented because they are much more difficult to obtain and code. This paper explores the suitability of transportation accident databases for use in human factors research. Given the goal of reducing the number and severity of transportation accidents, it is useful to use accident data as a tool to understand the common causes of accidents. Problems arise, however, because existing databases were typically not created explicitly for research purposes, and coding systems and file structures often omit or obscure useful information. Improved coding schemes and file structures that promote the use of databases for human factors research are discussed. Accident investigation methodologies that can improve the quality of human factors information in databases are also considered. Finally, problems associated with the use of existing databases are noted.

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