scholarly journals IMPROVING FPGA COMPONENTS OF CRITICAL SYSTEMS BASED ON NATURAL VERSION REDUNDANCY

2021 ◽  
Vol 4 (2) ◽  
pp. 168-177
Author(s):  
Oleksandr V. Drozd ◽  
Andrzej Rucinski ◽  
Kostiantyn V. Zashcholkin ◽  
Myroslav O. Drozd ◽  
Yulian Yu. Sulima
Keyword(s):  
Normal Mode ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Fault Tolerant ◽  
Normal Operation ◽  
Functional Safety ◽  
Critical Systems ◽  
Program Code ◽  
Field Programmable ◽  
Emergency Mode

The article is devoted to the problem of improving FPGA (Field Programmable Gate Array) components developed for safety related systems. FPGA components are improved in the checkability of their circuits and the trustworthiness of the results calculated on them to support fault-tolerant solutions, which are basic in ensuring the functional safety of critical systems. Fault-tolerant solu tions need protection from sources of multiple failures, which include hidden faults. They can be accumulated in significant quanti ties during a long normal operation and disrupt the functionality of fault-tolerant circuits with the onset of the most responsible emer gency mode. Protection against hidden faults is ensured by the checkability of the circuits, which is aimed at the manifestation of faults and therefore must be supported in conjunction with the trustworthiness of the results, taking into account the decrease in trustworthiness in the event of the manifestation of faults. The problem of increasing the checkability of the FPGA component in normal operation and the trustworthiness of the results calculated in the emergency mode is solved by using the natural version re dundancy inherent in the LUT-oriented architecture (Look-Up Table). This redundancy is manifested in the existence of many ver sions of the program code that preserve the functionality of the FPGA component with the same hardware implementation. The checkability of the FPGA component and the trustworthiness of the calculated results are considered taking into account the typical failures of the LUT-oriented architecture. These malfunctions are investigated from the standpoint of the consistency of their mani festation and masking, respectively, in normal and emergency modes on versions of the program code. Malfunctions are identified with bit distortion in the memory of the LUT units. Bits that are only observed in emergency mode are potentially dangerous because they can hide faults in normal mode. Moving potentially dangerous bits to checkable positions, observed in normal mode, is per formed by choosing the appropriate versions of the program code and organizing the operation of the FPGA component on several versions. Experiments carried out with the FPGA component using the example of an iterative array multiplier of binary codes have shown the effectiveness of using the natural version redundancy of the LUT-oriented architecture to solve the problem of hidden faults.

scholarly journals A SIMULATION MODEL FOR ROBOT’S SLIP DISPLACEMENT SENSORS

2016 ◽  
pp. 224-236 ◽  
Author(s):  
Yuriy Kondratenko ◽  
Oleksandr Gerasin ◽  
Andriy Topalov
Keyword(s):  
Simulation Model ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Displacement Sensor ◽  
Clamping Force ◽  
Sensing System ◽  
Displacement Sensors ◽  
Field Programmable ◽  
Slip Displacement ◽  
Corrosive Environments

This paper deals with a simulation model of slip displacement sensors for the object slip signals’ registration in the adaptive robot’s gripper. The study presents the analysis of different methods for slip displacement signals detection, as well as authors’ solutions. Special attention is paid to the investigations of the developed sensor with the resistive registration element in rod type structure of sensitive elements, which is able to operate in harsh and corrosive environments. A sensing system for the object slip signals’ registration in the adaptive robot’s gripper with a clamping force correction is developed for proposed slip displacement sensor with multi-component resistive registration elements. The hardware implementation of the sensing system for slip signals’ registration and obtained results are considered in details. The simulation model of the proposed slip displacement sensor based on polytypic conductive rubber is modeled by Proteus software. The intelligent approaches with the use of a field programmable gate array (FPGA) and VHDL-model to the sensing system designing allow to define the slippage direction in slip displacement sensor based on resistive registration elements. Thus, this expands the functionality of the developed sensor.

FPGA Technology and Platforms for NPP I&C systems

2020 ◽  
pp. 419-457
Author(s):  
Andriy Kovalenko ◽  
Ievgen Babeshko ◽  
Viktor Tokarev ◽  
Kostiantyn Leontiiev
Keyword(s):  
Field Programmable Gate Array ◽  
Nuclear Power ◽  
Power Plants ◽  
Critical Systems ◽  
Field Programmable ◽  
Assessment Techniques ◽  
Safety Critical Systems ◽  
New Generation ◽  
And Control ◽  
Element Base

This chapter describes an element base of new generation for NPP I&C, namely field programmable gate array (FPGA), and peculiarities of the FPGA application for designing safety critical systems. FPGA chips are modern complex electronic components that have been applied in nuclear power plants (NPPs) instrumentation and control systems (I&CSs) during the last 15-17 years. The advantages and some risks caused by application of the FPGA technology are analyzed. Safety assessment techniques of FPGA-based I&CSs and experience of their creation are described. The FPGA-based platform RadICS and its application for development of NPP I&CS is described.

Memristor Oscillators and its FPGA Implementation

2011 ◽  
Vol 383-390 ◽  
pp. 6992-6997 ◽  
Author(s):  
Ai Xue Qi ◽  
Cheng Liang Zhang ◽  
Guang Yi Wang
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Chaotic Attractor ◽  
Hardware Implementation ◽  
Fpga Implementation ◽  
Experimental Results ◽  
Linear Resistance ◽  
Non Linear ◽  
Field Programmable

This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.

scholarly journals Hardware implementation and performance analysis of MPTD-CSMA protocol based on field-programmable gate array in VANET

2020 ◽  
Vol 14 (16) ◽  
pp. 2769-2779
Author(s):  
Hongwei Ding ◽  
Xu Lu ◽  
Bo Li ◽  
Liqing Wang ◽  
Liyong Bao ◽  
...  
Keyword(s):  
Performance Analysis ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Field Programmable ◽  
Gate Array ◽  
And Performance

Field programmable gate array-based fault-tolerant hysteresis current control for AC machine drives

2012 ◽  
Vol 6 (3) ◽  
pp. 181 ◽  
Author(s):  
H. Berriri ◽  
W. Naoaur ◽  
I. Bahri ◽  
I. Slama-Belkhodja ◽  
E. Monmasson
Keyword(s):  
Field Programmable Gate Array ◽  
Fault Tolerant ◽  
Current Control ◽  
Hysteresis Current Control ◽  
Field Programmable ◽  
Gate Array ◽  
Machine Drives

scholarly journals Bubble-Proof Algorithm for Wave Union TDCs

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 30
Author(s):  
Paweł Kwiatkowski ◽  
Dominik Sondej ◽  
Ryszard Szplet
Keyword(s):  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Single Shot ◽  
Output Data ◽  
Data Encoding ◽  
Field Programmable ◽  
Output Code ◽  
Efficient Data ◽  
Fpga Chip

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

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