A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors

2017 ◽  
Vol 13 (3) ◽  
pp. 490-496
Author(s):  
Vinay Kumar ◽  
Krishna Lal Baishnab ◽  
Binod Kumar
2020 ◽  
Vol 2 (1) ◽  
pp. 79
Author(s):  
Fernando de Souza Campos ◽  
Bruno Albuquerque de Castro ◽  
Jacobus W. Swart

Several CMOS imager sensors were proposed to obtain high dynamic range imager (>100 dB). However, as drawback these imagers implement a large number of transistors per pixel resulting in a low fill factor, high power consumption and high complexity CMOS image sensors. In this work, a new operation mode for 3 T CMOS image sensors is presented for high dynamic range (HDR) applications. The operation mode consists of biasing the conventional reset transistor as active load to photodiode generating a reference current. The output voltage achieves a steady state when the photocurrent becomes equal to the reference current, similar to the inverter operation in the transition region. At a specific bias voltage, the output swings from o to Vdd in a small light intensity range; however, high dynamic range is achieve using multiple readout at different bias voltage. For high dynamic range operation different values of bias voltage can be applied from each one, and the signal can be captured to compose a high dynamic range image. Compared to other high dynamic range architectures this proposed CMOS image pixel show as advantage high fill-factor (3 T) and lower complexity. Moreover, as the CMOS pixel does not operate in integration mode, de readout can be performed at higher speed. A prototype was fabricated at 3.3 V 0.35 µm CMOS technology. Experimental results are shown by applying five different control voltage from 0.65 to 1.2 V is possible to obtain a dynamic range of about 100 dB.


Sensors ◽  
2019 ◽  
Vol 19 (9) ◽  
pp. 2073 ◽  
Author(s):  
Kazunari Kurita ◽  
Takeshi Kadono ◽  
Satoshi Shigematsu ◽  
Ryo Hirose ◽  
Ryosuke Okuyama ◽  
...  

We developed silicon epitaxial wafers with high gettering capability by using hydrocarbon–molecular–ion implantation. These wafers also have the effect of hydrogen passivation on process-induced defects and a barrier to out-diffusion of oxygen of the Czochralski silicon (CZ) substrate bulk during Complementary metal-oxide-semiconductor (CMOS) device fabrication processes. We evaluated the electrical device performance of CMOS image sensor fabricated on this type of wafer by using dark current spectroscopy. We found fewer white spot defects compared with those of intrinsic gettering (IG) silicon wafers. We believe that these hydrocarbon–molecular–ion–implanted silicon epitaxial wafers will improve the device performance of CMOS image sensors.


Sensors ◽  
2019 ◽  
Vol 19 (24) ◽  
pp. 5447
Author(s):  
Calvin Yi-Ping Chao ◽  
Shang-Fu Yeh ◽  
Meng-Hsu Wu ◽  
Kuo-Yu Chou ◽  
Honyih Tu ◽  
...  

In this paper we present a systematic approach to sort out different types of random telegraph noises (RTN) in CMOS image sensors (CIS) by examining their dependencies on the transfer gate off-voltage, the reset gate off-voltage, the photodiode integration time, and the sense node charge retention time. Besides the well-known source follower RTN, we have identified the RTN caused by varying photodiode dark current, transfer-gate and reset-gate induced sense node leakage. These four types of RTN and the dark signal shot noises dominate the noise distribution tails of CIS and non-CIS chips under test, either with or without X-ray irradiation. The effect of correlated multiple sampling (CMS) on noise reduction is studied and a theoretical model is developed to account for the measurement results.


Sensors ◽  
2019 ◽  
Vol 19 (24) ◽  
pp. 5534
Author(s):  
Yolène Sacchettini ◽  
Jean-Pierre Carrère ◽  
Romain Duru ◽  
Jean-Pierre Oddou ◽  
Vincent Goiffon ◽  
...  

Plasma processes are known to be prone to inducing damage by charging effects. For CMOS image sensors, this can lead to dark current degradation both in value and uniformity. An in-depth analysis, motivated by the different degrading behavior of two different plasma processes, has been performed in order to determine the degradation mechanisms associated with one plasma process. It is based on in situ plasma-induced charge characterization techniques for various dielectric stack structures (dielectric nature and stack configuration). A degradation mechanism is proposed, highlighting the role of ultraviolet (UV) light from the plasma in creating an electron hole which induces positive charges in the nitride layer at the wafer center, and negative ones at the edge. The trapped charges de-passivate the SiO2/Si interface by inducing a depleted interface above the photodiode, thus emphasizing the generation of dark current. A good correlation between the spatial distribution of the total charges and the value of dark current has been observed.


Sign in / Sign up

Export Citation Format

Share Document