Low Voltage, Low Power Gm-C Filter for Low Frequency Applications

2018 ◽  
Vol 14 (2) ◽  
pp. 266-274 ◽  
Author(s):  
G. Hanumantha Rao ◽  
S. Rekha
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Low Frequency

A Low Power Amplifier for Bio-Signal Processing

2011 ◽  
Vol 108 ◽  
pp. 289-293
Author(s):  
Tao Zhou
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
Power Amplifier ◽  
Low Voltage ◽  
Low Frequency ◽  
Low Noise ◽  
Cmos Process ◽  
Very Low Frequency ◽  
Voltage Amplifier

This paper presents a low voltage amplifier with low noise and very low frequency designed for bio-signal processing. The amplifier requires only ± 0.6V supply and consumes 1.24μW, with a 75.5 dB gain over a bandwidth covering a range of frequencies from some hundreds of mHz to 19 kHz. A SMIC 0.13μm CMOS process is used in design and simulation.

Design of a Low-Voltage Low-Power CMOS Operational Amplifier

2013 ◽  
Vol 380-384 ◽  
pp. 3283-3286
Author(s):  
Lin Hai Cui ◽  
Rui Xu ◽  
Zhan Peng Jiang ◽  
Chang Chun Dong
Keyword(s):  
Low Power ◽  
Operational Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Low Frequency ◽  
Open Loop ◽  
Common Source ◽  
Output Stage ◽  
Input Stage ◽  
Current Mirrors

A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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