Linear Integrated Circuit Design in the Curriculum

1982 ◽  
Vol 19 (3) ◽  
pp. 265-270
Author(s):  
H. E. Hanrahan ◽  
S. J. West
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Common Ground ◽  
Digital Circuit ◽  
Digital Design ◽  
Integrated Circuit Design ◽  
Digital Circuit Design ◽  
Basic Concepts ◽  
Tools And Techniques

Recent advances in VLSI digital circuit design methods and the silicon foundry concept has put the design of such circuits within reach of students. This paper discusses the design of linear integrated circuits by students. The basic concepts, tools and techniques are reviewed. The areas of common ground and differences between analogue and digital design techniques are highlighted.

A Novel Technique for Arithmetic Elements Standard Cell Library Establishment Based on Tanner Tools

2012 ◽  
Vol 569 ◽  
pp. 273-276
Author(s):  
Chun Zhao ◽  
Ce Zhou Zhao ◽  
Bin Da
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Standard Cell ◽  
Integrated Circuit Design ◽  
Standard Cell Library ◽  
Cell Library ◽  
Complete Circuit

The economic and efficient accomplishment of an application-specific integrated circuit design depends heavily upon the choice of the library. Therefore, it is important to build library that full fills the design requirement. Tanner Tools is a set of software for designing integrated circuits. The great advantage of Tanner is that it can provide a complete circuit design tools in desktop computers. The paper aims to create a standard cell library establishment on the 0.5 micro complementary metal–oxide–semiconductor mixed signal process based on the Tanner Tools.

scholarly journals Novel Design of Reversible MUX and DEMUX using GDI Techinque

2015 ◽  
Vol 4 (3) ◽  
pp. 103
Author(s):  
Majety Naveenkumar
Keyword(s):  
Power Consumption ◽  
Circuit Design ◽  
Digital Circuits ◽  
Reducing Power ◽  
Digital Circuit ◽  
Digital Design ◽  
Digital Circuit Design ◽  
Fredkin Gate ◽  
Reversible Gate ◽  
Novel Design

Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively  and these are developed by using only one type of Reversible gate i.e. Fredkin Gate (FRG) and Not Gate. The simulations are done in H-Spice using 90nm technology.

Power and Ground Metal Insertion into Integrated Circuit Design Combined with Timing Aware Dummy Metal Fill Insertion

2021 ◽  
Vol 26 (3-4) ◽  
pp. 226-233
Author(s):  
S.S. Abazyan ◽  
◽  
V.Sh. Melikyan ◽  
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Integrated Circuit Design ◽  
New Approach ◽  
Ir Drop ◽  
Coupling Capacitance ◽  
Placement And Routing ◽  
Metal Ratio ◽  
Metal Insertion

As dummy metal fill insertion is mandatory step for integrated circuits’ (IC) current manufacturing processes, many works are targeting better fill insertion with small coupling capacitance. However, with scaling technology trends, smaller IR drop is becoming more and more required, as its high value can lead to integrated circuit working failures. To ensure IR drop reduction, a new approach was proposed: while doing dummy fill insertion, firstly, metal shapes which are tied to power and ground nets were inserted and then timing aware dummy metal shapes were added. It has been established that power and ground metal fill shapes were creating shield layers, hence optimizing IR drop. Later it was found that timing aware dummy metal fill insertion was creating dummy metals for ensuring final metal ratio. Experiments have shown that with the use of proposed method, for 5 different designs IR drop has been reduced on average by about 11,9 %; however, placement and routing tool runtime has been increased by about 27,8 % and overall capacitance has been increased by about 4,4 %.

A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

2007 ◽  
Author(s):  
Hung-Sung Lin ◽  
Ying-Chin Hou ◽  
Juimei Fu ◽  
Mong-Sheng Wu ◽  
Vincent Huang ◽  
...  
Keyword(s):  
Liquid Crystal ◽  
Circuit Design ◽  
Process Design ◽  
Integrated Circuit ◽  
Photon Emission ◽  
Integrated Circuit Design ◽  
Nano Scale ◽  
Leakage Path ◽  
Related Defect

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

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