A Novel Technique for Arithmetic Elements Standard Cell Library Establishment Based on Tanner Tools

2012 ◽  
Vol 569 ◽  
pp. 273-276
Author(s):  
Chun Zhao ◽  
Ce Zhou Zhao ◽  
Bin Da
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Standard Cell ◽  
Integrated Circuit Design ◽  
Standard Cell Library ◽  
Cell Library ◽  
Complete Circuit

The economic and efficient accomplishment of an application-specific integrated circuit design depends heavily upon the choice of the library. Therefore, it is important to build library that full fills the design requirement. Tanner Tools is a set of software for designing integrated circuits. The great advantage of Tanner is that it can provide a complete circuit design tools in desktop computers. The paper aims to create a standard cell library establishment on the 0.5 micro complementary metal–oxide–semiconductor mixed signal process based on the Tanner Tools.

Considerations on the de-embedding of differential devices using two-port techniques

2010 ◽  
Vol 2 (3-4) ◽  
pp. 349-357 ◽  
Author(s):  
Vadim Issakov ◽  
Maciej Wojnowski ◽  
Andreas Thiede ◽  
Robert Weigel
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
High Frequency ◽  
Mode Conversion ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Integrated Circuit Design ◽  
Differential Signaling ◽  
On Chip

Differential signaling is very common for high frequency integrated circuit design. Accurate multimode de-embedding at multigigahertz frequencies, however, is a major challenge. The differential and common-mode parameters can be obtained by converting the measured four-port nodal S-parameters into the mixed-mode form. Under certain conditions, it is possible to separate the modes and consider only the entries corresponding to the differential S-parameters. This allows to reduce the measured 4 × 4 matrix to a 2 × 2 matrix and consider the differential device as a two-port network. Thus, the standard de-embedding techniques, derived for two-port networks, can be applied to differential S-parameters. The purpose of this paper is to investigate the applicability of this approach for on-wafer measurements. We describe analytically the conditions under which this method is valid. As an example, a 2:1 transformer, manufactured in Infineon's 0.13 μm CMOS (complementary metal-oxide semiconductor) process, has been characterized. On-chip de-embedding structures have been fabricated using the same process. The results obtained using Short-Open, Thru-Line, and Thru-Line-Reflect de-embedding techniques are compared. Additionally, the results are verified by simulation of a device under test having high-mode conversion.

Linear Integrated Circuit Design in the Curriculum

1982 ◽  
Vol 19 (3) ◽  
pp. 265-270
Author(s):  
H. E. Hanrahan ◽  
S. J. West
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Common Ground ◽  
Digital Circuit ◽  
Digital Design ◽  
Integrated Circuit Design ◽  
Digital Circuit Design ◽  
Basic Concepts ◽  
Tools And Techniques

Recent advances in VLSI digital circuit design methods and the silicon foundry concept has put the design of such circuits within reach of students. This paper discusses the design of linear integrated circuits by students. The basic concepts, tools and techniques are reviewed. The areas of common ground and differences between analogue and digital design techniques are highlighted.

A Novel Approach to Unsupervised Automated Extraction of Standard Cell Library for Reverse Engineering and Hardware Assurance

2019 ◽  
Author(s):  
Ronald Wilson ◽  
Rabin Y. Acharya ◽  
Domenic Forte ◽  
Navid Asadizanjani ◽  
Damon Woodard
Keyword(s):  
Reverse Engineering ◽  
Integrated Circuit ◽  
Contact Layer ◽  
Layer By Layer ◽  
Standard Cell ◽  
High Definition ◽  
Standard Cell Library ◽  
Cell Library ◽  
Standard Cells ◽  
Novel Approach

Abstract Reverse engineering today is supported by several tools, such as ICWorks, that assist in the processing and extraction of logic elements from high definition layer by layer images of integrated circuits. To the best of our knowledge, they all work under the assumption that the standard cell library used in the design process of the integrated circuit is available. However, in situations where reverse engineering is done on commercial off-the-shelf components, this information is not available thereby, rendering the assumption invalid. Until now, this problem has not been addressed. In this paper, we introduce a novel approach for the extraction of standard cell library using the contact layer from these images. The approach is completely automated and does not require any prior knowledge on the construction or layout of the target semiconductor integrated circuit. The performance of the approach is evaluated on two AES designs with 10,000 cells compiled from standard libraries with 32nm and 90nm node technologies having 350 and 340 standard cells respectively. We were able to successfully extract 94% and 60% of the standard cells from the 32nm and 90nm AES designs using the proposed approach. We also perform a case study using a realworld sample extracted from a smartcard. Finally, we also investigate the various challenges involved in the extraction of standard cells from images and the steps involved in resolving them.

Minimization of Leakage Currents in Dram 4x4 Using SVL Technique

2021 ◽  
pp. 221-228
Author(s):  
N. Geetha Rani ◽  
C. Soundarya Lahari ◽  
G. Revathi ◽  
K. Chandrika ◽  
G. Riya
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Integrated Circuit ◽  
Heat Dissipation ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Oxide Semiconductor ◽  
Portable Devices ◽  
Leakage Currents

In recent years, due to development of integrated circuits technology, power is being given comparable weight to area and speed considerations. The power consumed for any given function in any complementary metal-oxide-semiconductor (CMOS) circuit must be reduced for either of the two different reasons. One is to reduce heat dissipation in order to allow a large density of functions to be incorporated on an Integrated Circuit (IC) chip. Any amount of power dissipation is worthwhile as long as it does not degrade overall circuit performance. The other reason is to save energy in battery operated instruments like in electronic watches where average power is in microwatts. Low power is the major issue not only in portable devices but also in non-portable devices. So, it is apparent that one has to resolve low power design methodologies for the design of high throughput, low power digital systems. By using this SVL technique using DRAM we are going to reduce the leakage currents and also improves the performance of the circuit.

Power and Ground Metal Insertion into Integrated Circuit Design Combined with Timing Aware Dummy Metal Fill Insertion

2021 ◽  
Vol 26 (3-4) ◽  
pp. 226-233
Author(s):  
S.S. Abazyan ◽  
◽  
V.Sh. Melikyan ◽  
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Integrated Circuit Design ◽  
New Approach ◽  
Ir Drop ◽  
Coupling Capacitance ◽  
Placement And Routing ◽  
Metal Ratio ◽  
Metal Insertion

As dummy metal fill insertion is mandatory step for integrated circuits’ (IC) current manufacturing processes, many works are targeting better fill insertion with small coupling capacitance. However, with scaling technology trends, smaller IR drop is becoming more and more required, as its high value can lead to integrated circuit working failures. To ensure IR drop reduction, a new approach was proposed: while doing dummy fill insertion, firstly, metal shapes which are tied to power and ground nets were inserted and then timing aware dummy metal shapes were added. It has been established that power and ground metal fill shapes were creating shield layers, hence optimizing IR drop. Later it was found that timing aware dummy metal fill insertion was creating dummy metals for ensuring final metal ratio. Experiments have shown that with the use of proposed method, for 5 different designs IR drop has been reduced on average by about 11,9 %; however, placement and routing tool runtime has been increased by about 27,8 % and overall capacitance has been increased by about 4,4 %.

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